MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1424

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
An example traversal of a periodic schedule that includes FSTNs is illustrated in
In frame N (micro-frames 0-7), for this example, the host controller traverses all of the schedule data
structures utilizing the Normal Path Link Pointers in any FSTNs it encounters. This is because the host
controller has not yet encountered a Save-Place FSTN so it is not executing in Recovery Path mode. When
it encounters the Restore FSTN, (Restore-N), during micro-frames 0 and 1, it uses Restore-N. Normal Path
Link Pointer to traverse to the next data structure (that is, normal schedule traversal). This is because the
host controller must use a Restore FSTN's Normal Path Link Pointer when not executing in a
Recovery-Path mode. The nodes traversed during frame N include: {8
1
In frame N+1 (micro-frames 0 and 1), when the host controller encounters Save-Path FSTN (Save-N), it
observes that Save-N.Back Path Link Pointer.T-bit is zero (definition of a Save-Path indicator). The host
controller saves the value of Save-N. Normal Path Link Pointer and follows Save-N.Back Path Link
21-90
0
...}.
•
Micro-Frames 0, 1
Normal Traversal
Normal Traversal
IN or an OUT). Refer to the EHCI Specification for a complete list of additional conditions that
must be met in general for the host controller to issue a bus transaction. Note that the host controller
must not execute a Start-split transaction while executing in Recovery Path mode. Refer to the
EHCI Specification for special handling when in Recovery Path mode.
Stop traversing the recovery path when it encounters an FSTN that is a Restore indicator. The host
controller unconditionally uses the saved value of the Save-Place FSTN's Normal Path Link
Pointer when returning to the normal path traversal. The host controller must clear the context of
executing a Recovery Path when it restores schedule traversal to the Save-Place FSTN's Normal
Path Link Pointer.
If the host controller determines that there is not enough time left in the micro-frame to complete
processing of the periodic schedule, it abandons traversal of the recovery path, and clears the
context of executing a recovery path. The result is that at the start of the next consecutive
micro-frame, the host controller starts traversal at the frame list.
for Frame N+1
for Frame N
Figure 21-54. Example Host Controller Traversal of Recovery Path via FSTNs
Frame Numbers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
N+5
N+4
N+3
N+1
N–1
N–2
N
83.0
82.0
87
86
85
84
81
80
83.1
82.1
Save = N
83.2
82.2
T-Int = 0
82.3
N-Ptr
B-Ptr
43
42
41
40
2.0
, 8
Causes ‘Restore’
2.1
to Normal Path
, 8
21
20
2.2
Traversal
, 8
Figure
N-Ptr
B-Ptr
Restore = N
2.3
Freescale Semiconductor
Recovery Path
Traversal
, 4
2
21-54.
T-Int = 1
, 2
10
0
, Restore-N,
• • •