MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 751

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
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— 10/100 Mbps RGMII
— 1000 Mbps full-duplex RGMII and RTBI
— 10/100 Mbps SGMII
— 1000 Mbps full-duplex SGMII
— 1000 Mbps IEEE 802.3z TBI
— Single-clock TBI
Support for two full-duplex FIFO interface modes
— 8-bit mode—GMII style and encoded packet
— Inter-packet and intra-packet flow control
— Optional CRC-32 generation and checking
— Minimal glue logic required to support POS PHY Level 3 conversion
— TCP/IP off-load and QoS features available in all FIFO modes
TCP/IP off-load
— IP v4 and IP v6 header recognition on receive
— IP v4 header checksum verification and generation
— TCP and UDP checksum verification and generation
— Per-packet configurable off-load
— Recognition of VLAN, stacked-VLAN, 802.2, PPPoE session, MPLS stacks, ARP, and
Quality of service (QoS) support
— Transmission from up to eight queues
— Reception to up to eight physical queues
Interrupt coalescing
— Packet-count-based thresholds for both receive and transmit
— Timer-based thresholds
Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
ESP/AH IP-Security headers
– Priority-based queue selection
– Modified weighted round-robin queue selection with fair bandwidth allocation
– 64 virtual receive queues overlaid on 8 physical buffer descriptor rings
– Table-oriented queue filing strategy based on 16 header fields or flags
– Frame rejection support for filtering applications
– Filing based on Ethernet, IP, and TCP/UDP properties, including VLAN fields, Ether-type,
programmed PAUSE frame generation and recognition)
IEEE 802.1 virtual local area network (VLAN) tags and priority
IP protocol type, IP TOS or differentiated services, IP source and destination addresses,
TCP/UDP port numbers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Enhanced Three-Speed Ethernet Controllers
14-3