MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1392

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21-58
31–28
26–16
13–12
31–30
29–23
22–16
11–8
Bits
Bits
6–0
27
15
14
7
Device Address Selects the specific device serving as the data source or sink.
Packet Length
Port Number
Maximum
Hub Addr
Name
EndPt
Name
EPS
Mult
RL
dtc
C
H
I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-56. Endpoint Characteristics: Queue Head DWord 1
Nak count reload. This field contains a value, which is used by the host controller to reload the Nak
Counter field.
Control endpoint flag. If the QH[EPS] field indicates the endpoint is not a high-speed device, and the
endpoint is a control endpoint, then software must set this bit to a one. Otherwise, it should always
set this bit to a zero.
This directly corresponds to the maximum packet size of the associated endpoint
(wMaxPacketSize). The maximum value this field may contain is 0x400 (1024).
Head of reclamation list flag. This bit is set by system software to mark a queue head as being the
head of the reclamation list.
Data toggle control (DTC). Specifies where the host controller should get the initial data toggle on
an overlay transition.
0 Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head.
1 Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the queue
Endpoint speed. This is the speed of the associated endpoint.
00 Full-speed (12 Mbps)
01 Low-speed (1.5 Mbps)
10 High-speed (480 Mbps)
11 Reserved, should be cleared This field must not be modified by the host controller.
Endpoint number. Selects the particular endpoint number on the device serving as the data source
or sink.
Inactivate on next transaction. This bit is used by system software to request that the host controller
set the Active bit to zero. This field is only valid when the queue head is in the periodic schedule and
the EPS field indicates a full- or low-speed endpoint. Setting this bit when the queue head is in the
asynchronous schedule or the EPS field indicates a high-speed device yields undefined results.
High-bandwidth pipe multiplier. This field is a multiplier used to key the host controller as the number
of successive packets the host controller may submit to the endpoint in the current execution. The
host controller makes the simplifying assumption that software properly initializes this field
(regardless of location of queue head in the schedules or other run time parameters).
00 Reserved, should be cleared. A zero in this field yields undefined results.
01 One transaction to be issued for this endpoint per micro-frame
10 Two transactions to be issued for this endpoint per micro-frame
11 Three transactions to be issued for this endpoint per micro-frame
This field is ignored by the host controller unless the EPS field indicates a full- or low-speed device.
The value is the port number identifier on the USB 2.0 hub (for hub at device address Hub Addr
below), below which the full- or low-speed device associated with this endpoint is attached. This
information is used in the split-transaction protocol.
This field is ignored by the host controller unless the EPS field indicates a full-or low-speed device.
The value is the USB device address of the USB 2.0 hub below which the full- or low-speed device
associated with this endpoint is attached. This field is used in the split-transaction protocol.
Table 21-57. Endpoint Capabilities: Queue Head DWord 2
head from the DT bit in the qTD.
Description
Description
Freescale Semiconductor