MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1312

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.5.1
The eSDHC uses one configurable data buffer so that data can be transferred between the internal system
bus (register bus or CCB bus) and the SD card in an optimized manner to maximize throughput between
the two clock domains (the IP peripheral clock and the master clock). See
of the buffer scheme.
The buffer is used as temporary storage for data being transferred between the host system and the card.
The burst lengths for read and write are both configurable and can be any value between 1 and 128 words.
For a host read operation, when the amount of data exceeds the RD_WML value, the eSDHC sets
PRSSTAT[BREN] and either:
Conversely, for a host write operation, when the amount of buffer spaces exceeds the WR_WML value,
the eSDHC sets PRSSTAT[BWEN] and either:
20.5.1.1
There are two ways to write data into the buffer when the user transfers data to the card:
When the internal DMA is not used (XFERTYP[DMAEN] is not set when the command is sent), the
eSDHC asserts an external DMA request when more than WML[WR_WML] number of empty buffer
word slots are available and ready for receiving new data. At the same time, the eSDHC sets
IRQSTAT[BWR]. The buffer write ready interrupt is generated if it is enabled by software.
20-38
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Issues a DMA request to inform the system to read the data
Issues a DMA interrupt to inform the system to read the data
When granted CCB access permission, the internal DMA burst-reads RD_WML number of words
Issues a DMA request to inform the system to write data to the buffer
Issues a DMA interrupt to inform the system to write data to the buffer
When granted CCB access permission, the internal DMA burst-writess WR_WML number of
words into the buffer
Processor core polling IRQSTAT[BWR] (interrupt or polling)
Internal DMA
Data Buffer
Write Operation Sequence
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Interface
Interface
Register
Logic
CCB
Bus
Figure 20-21. eSDHC Buffer Scheme
Internal
Internal
Internal
DMA
DMA
DMA
eSDHC Registers
eSDHC Registers
eSDHC Registers
Buffer Control
Buffer Control
Buffer Control
Wrapper
Wrapper
Wrapper
Buffer
Buffer
Buffer
RAM
RAM
RAM
TxFIFO
TxFIFO
TxFIFO
RxFIFO
RxFIFO
RxFIFO
Status
Status
Status
FIFOs
FIFOs
FIFOs
Sync
Sync
Sync
Sync
Sync
Sync
Figure 20-21
Interface
Interface
Interface
SD Bus
SD Bus
SD Bus
Freescale Semiconductor
for an illustration