MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 802

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset eTSEC1:0x2_4300;
Reset
Reset
Enhanced Three-Speed Ethernet Controllers
14.5.3.3.1
The RCTRL register is programmed by the user and controls the operational mode of the receiver. It must
be written only after a system reset (at initialization) or after a graceful receive stop has completed.
Figure 14-24
Table 14-29
14-54
W
W
11–15
R
R
8–10
Bits
0–6
7
eTSEC3:0x2_6300
—
16
0
L2OFF
Name
LFC VLEX FILREN FSQEN GHTX IPCSEN TUCSEN
PAL
17
TS
—
describes the fields of the RCTRL register.
describes the RCTRL register.
Receive Control Register (RCTRL)
18
Layer 2 offset. The number of octet pairs from the start of the frame that the parser should expect to see
before the first byte of the Ethernet DA.
For frames received over Ethernet, the start of frame is regarded as the SFD symbol.
For packets received through the FIFO packet interface the start of frame is regarded as the first octet of
receive data.
The user may think of this value as representing the length - in multiples of two bytes - of a ‘shim’ header
that is inserted between the SFD and DA. By writing to RCTRL with a mask of 0xFE00_0000, the even
byte length restriction is guaranteed.
For normal frames, this field should be left as 0.
Time stamp incoming packets as padding bytes. PAL field is set to 8 if the PAL field is programmed to less
than 8. Must be set to zero if TMR_CTRL[TE]=0.
Reserved
Packet alignment padding length. If not zero, PAL (1–31) bytes of zero padding are inserted before the
start of each received frame, but following the RxFCB if TOE is enabled. For Ethernet where optional
preamble extraction is enabled, the padding appears before the preamble, otherwise the padding
precedes the layer 2 header. The value of PAL can be set so that the start of the IP header in the receive
data buffer is aligned to a 32-bit boundary. Normally, setting PAL = 2 provides minimal padding to ensure
such alignment of the IP header.
Note that the minimum zero padding value for this field should be PAL–8 if the TS field is set and 0 when
PAL is < 8.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
19
L2OFF
20
Figure 14-24. RCTRL Register Definition
Table 14-29. RCTRL Field Descriptions
21
22
All zeros
All zeros
TS
23
7
Description
24
PRSDEP
8
25
—
PRSFM BC_REJ PROM RSF EMEN —
10
26
11
27
Freescale Semiconductor
28
Access: Read/Write
PAL
29
30
15
31