MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1337

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
USB n _PWRFAULT
USB n _PCTL0
USB n _PCTL1
USB n _NXT
USB n _STP
USB n _DIR
Signal
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
I/O
O Stop. USB n _STP indicates the end of a transfer on the bus.
O Port control 0. USB n _PCTL0 controls the port status indicator LED 0 when in host mode.
O Port control 1. USB n _PCTL1 controls the port status indicator LED 1 when in host mode.
I
I
I
to USB port, it drives USB n _DIR high to take ownership of the bus. When the PHY has no data
to transfer it drives USB n _DIR low and monitors the bus for link activity. The PHY pulls
USB n _DIR high whenever the interface cannot accept data from the link.
to the PHY, USB n _NXT indicates when the current byte has been accepted by the PHY. The
USB port places the next byte on the data bus in the following clock cycle. When the PHY is
sending data to USB port, USB n _NXT indicates when a new byte is available for USB port to
consume.
Power fault. USB n _PWRFAULT indicates whether a power fault occurred on the USB port
Vbus.
Note: USB n _PWRFAULT, only exists for USB1 and USB2, not for USB3.
Note: USB n _PCTL0, only exists for USB1 and USB2, not for USB3.
Note: USB n _PCTL1, only exists for USB1 and USB2, not for USB3.
Direction. USB n _DIR controls the direction of the data bus. When the PHY has data to transfer
Next data. The PHY asserts USB n _NXT to throttle the data. When USB port is sending data
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing
Timing
Timing Synchronous to PHY_CLK.
Timing Synchronous to PHY_CLK.
Timing Synchronous to PHY_CLK.
Timing Synchronous to PHY_CLK.
State
State
State
State
State
State
Table 21-1. ULPI Signal Descriptions
Asserted—PHY has data to transfer to the link.
Negated—PHY has no data to transfer.
Asserted—PHY is ready to transfer byte.
Negated—PHY is not ready.
Asserted—USB asserts this signal for 1 clock cycle to stop the data stream
Negated—Indicates normal operation.
Asserted—Indicates that a Vbus fault occurred. Applications that support power
Negated—Indicates normal operation.
Asserted—LED on.
Negated—LED off.
Synchronous to PHY_CLK.
Asserted—LED on.
Negated—LED off.
Synchronous to PHY_CLK.
currently on the bus. If USB port is sending data to the PHY, USB n _STP
indicates the last byte of data was previously on the bus. If the PHY is
sending data to USB port, USB n _STP forces the PHY to end its transfer,
negate USB n _DIR and relinquish control of the data bus to the USB port.
switching must shut down Vbus power.
Description
Universal Serial Bus Interfaces
21-3