MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 259

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.9.6
The L2 cache supports error checking and correcting (ECC) for the data path between the core master and
system memory. It detects all double-bit errors, detects all multi-bit errors within a nibble, and corrects all
single-bit errors. Other errors may be detected, but are not guaranteed to be corrected or detected.
Multiple-bit errors are always reported when error reporting is enabled. When a single-bit error occurs, the
single-bit error counter register is incremented, and its value compared to the single-bit error trigger register.
An error is reported when these values are equal. The single-bit error registers can be programmed such that
minor memory faults are corrected and ignored, but double- or multi-bit errors generate an interrupt.
The syndrome encodings for the ECC code are shown in
Freescale Semiconductor
Data
Bit
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
1
2
3
4
5
6
7
8
9
Error Checking and Correcting (ECC)
0
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•
•
•
•
•
•
•
•
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•
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MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
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2
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Syndrome Bit
Table 6-29. L2 Cache ECC Syndrome Encoding
3
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4
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•
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•
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5
•
•
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•
•
•
•
•
•
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6
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7
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Table 6-29
Data
Bit
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
0
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•
•
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and
1
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Table
2
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Syndrome Bit
6-30.
3
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L2 Look-Aside Cache/SRAM
4
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•
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5
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•
•
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6
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7
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6-39