MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1153

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.8.2.8
This register does not apply to PCI Express. It is present for legacy purposes.
17.3.8.3
The type 1 header is shown in
Section 17.3.8.1, “Common PCI Compatible Configuration Header
the first 16 bytes of the header. This section describes the registers that are unique to the type 1 header
beginning at offset 0x10.
Freescale Semiconductor
Offset 0x3F (EP-mode only)
Reset
Bits
W
7–0
Reserved
R
Secondary Latency Timer
MAX_LAT Does not apply for PCI Express.
7
Name
BIST
Type 1 Configuration Header
PCI Express Maximum Latency Register (EP-Mode Only)—0x3F
Prefetchable Memory Limit
Figure 17-58. PCI Express PCI-Compatible Configuration Header—Type 1
I/O Limit Upper 16 Bits
Table 17-56. PCI Express Maximum Latency Register Field Description
Secondary Status
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 17-57. PCI Express Maximum Latency Register (MAX_LAT)
Bridge Control
Memory Limit
Device ID
Status
Subordinate Bus Number
Figure
Header Type
Class Code
Prefetchable Base Upper 32 Bits
Prefetchable Limit Upper 32 Bits
17-58.
Base Address Register 0
MAX_LAT
All zeros
Secondary Bus Number
Latency Timer
Description
Interrupt Pin
I/O Limit
Prefetchable Memory Base
I/O Base Upper 16 Bits
Registers,” describes the registers in
Memory Base
Command
Vendor ID
Primary Bus Number
Capabilities Pointer
PCI Express Interface Controller
Cache Line Size
Interrupt Line
Revision ID
I/O Base
Access: Read only
Offset (Hex)
Address
0
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
3C
17-57