MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 585

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.7.10.2 PKEU Parameter Memory B
This 4096-bit memory is used typically as an input parameter memory space, as well as the result memory
space. For modular arithmetic routines, this memory operates as one of the operands of the desired
function, as well as the result memory space. For elliptic curve routines, this memory is segmented in to
four 1024 bit memories, and is used to specify particular curve parameters and input values, as well as to
store result values.
10.7.7.10.3 PKEU Parameter Memory E
This 4096-bit memory is non-segmentable, and specifies the exponent for modular exponentiation, or the
multiplier k for elliptic curve point multiplication. This memory space is write only; a read of this memory
space causes address error to be reflected in the PKEU interrupt status register.
10.7.7.10.4 PKEU Parameter Memory N
This 4096-bit memory is non-segmentable, and specifies the modulus for modular arithmetic and F
elliptic curve routines. For F
10.7.8
This section contains details about the random number generator unit, including modes of operation, status
and control registers, and FIFO.
The RNGU is an execution unit capable of generating 64-bit random numbers. It contains a True Random
Number Generator (TRNG).The RNGU is designed to comply with the FIPS-140 standard for randomness
and non-determinism.
The RNGU consists of five major functional blocks:
The states of the LFSRs in the TRNG are advanced at an unknown frequency determined by the ring
oscillator clock. The entropy generated by this structure is then added into the XKEY structure of the
PRNG during seed generation. Seed generation takes approximately 2,000,000 cycles as 20,000 bits of
entropy are sampled from the output of the LFSRs of the TRNG.
After the initial seeding, the RNGU turns off the TRNG and uses solely the PRNG to generate random
data. After 1,000,000 times through the algorithm the RNGU is once again seeded. This second seed
occurs the next time through the algorithm by using data from the Simultaneous Reseed LFSR to modify
the algorithm. The data in the simultaneous reseed LFSR comes directly from the TRNG as well and was
being generated during the first 20,000 times through the PRNG algorithm after the initial seed was
completed.
Freescale Semiconductor
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64-bit internal bus interface, registers, and FIFO
True Random Number Generator (ring oscillator, LFSRs, Statistical Checker)
Xseed Generator
Pseudo-Random Number Generator (XKEY, SHA-1, FSM)
Simultaneous Reseed LFSR
Random Number Generator Unit (RNGU)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
m elliptic curve routines, this memory specifies the irreducible polynomial.
Security Engine (SEC) 3.0
p
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