MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 576

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
If SHA-384 or SHA-512 are selected, then each of the registers A, B, C, D, E, F, G, H are 64-bits (instead
of 32 bits for other hash algorithms). As a result, the base address for each context register is shifted to
adjust.
10.7.6.13 MDEU Key Registers
The MDEU maintains sixteen 64-bit registers for writing an HMAC key; only the first eight are used for
MD5, SHA-1, SHA-224, or SHA-256. The IPAD and OPAD operations are performed automatically on
the key data when required.
10.7.6.14 MDEU FIFOs
MDEU uses an input FIFO to hold data to be hashed (followed in some case by an ICV
value for ICV checking). Normally, the channels control all access to this FIFO. For
host-controlled operation, a write to anywhere in the MDEU FIFO address space enqueues data to the
MDEU input FIFO, and a read from anywhere in this address space returns all zeros.
When the host writes to the MDEU FIFO (using host-controlled access), it can write to any FIFO address
by byte, word (4 bytes), or dword (8 bytes). The MDEU assembles these bytes from left to right, so that
the first bytes written are placed in the most significant bit-positions. Whenever the MDEU accumulates
8 bytes, this dword is automatically enqueued into the FIFO, and any remaining bytes are left-justified in
preparation for assembling the next dword. It is not necessary to fill all bytes of the final dword. Any last
bytes remaining in the staging register are automatically padded with zeros and forced into the input FIFO
when the MDEU end of message register is written.
Overflows caused by writing the MDEU FIFO are reflected in the MDEU interrupt status register.
10.7.7
This section contains details about the public key execution unit (PKEU), including modes of operation,
status and control registers, and parameter RAMs.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the PKEU is used through channel-controlled access,
which means that most reads and writes of PKEU registers are directed by the SEC channels. Driver
software would perform host-controlled register accesses only on a few registers for initial configuration
and error handling.
10-146
Public Key Execution Units (PKEU)
All SHA algorithms are big endian. MD5 is little endian. The MDEU
module internally reverses the endianness of the key upon writing to or
reading from the MDEU key registers if the MDEU mode register indicates
MD5 is the hash of choice.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Freescale Semiconductor