MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1472

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.8.5
21.8.5.1
It is necessary for the DCD software to maintain head and tail pointers to the for the linked list of dTDs
for each respective queue head. This is necessary because the dQH only maintains pointers to the current
working dTD and the next dTD to be executed. The operations described in next section for managing dTD
will assume the DCD can use reference the head and tail of the dTD linked list.
21.8.5.2
Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. Use the
following procedure for building dTDs.
Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit address 4–0 would
be equal to ‘00000’
Write the following fields:
21-138
4. Decode setup packet and prepare data phase [optional] and status phase transfer as required by the
1. Initialize first 7 DWords to 0.
2. Set the terminate bit to ‘1.’
3. Fill in total bytes with transfer size.
4. Set the interrupt on complete if desired.
5. Initialize the status field with the active bit set to ‘1’ and all remaining status bits set to ‘0.’
USB Chapter 9 or application specific protocol.
Managing Transfers with Transfer Descriptors
Software Link Pointers
Building a Transfer Descriptor
It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress
must be flushed and the new control packet completed.
To conserve memory, the reserved fields at the end of the dQH can be used
to store the Head and Tail pointers but it still remains the responsibility of
the DCD to maintain the pointers.
Head Pointer
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Completed dTDs
Figure 21-64. Software Link Pointers
Endpoint QH
Current
NOTE
NOTE
Queued dTDs
Next
Tail Pointer
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