MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1207

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Transaction
response
response
response
response
response
response
response
response
response
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
Inbound
Type
PEX response time out. This case
happens when the internal
platform sends a non-posted
request that did not get a response
back after a specific amount of time
specified in the outbound
completion timeout register
(PEX_OTB_CPL_TOR)
Unexpected PEX response. This
can happen if, after the response
times out and the internal queue
entry is deallocated, the response
comes back.
Unsupported request (UR)
response status
Completer abort (CA) response
status
Poisoned TLP (EP=1)
ECRC error
Configuration Request Retry
Status (CRS) timeout for a
configuration transaction that
originates from
PEX_CONFIG_ADDR/
PEX_CONFIG_DATA
UR response for configuration
transaction that originates from
PEX_CONFIG_ADDR/
PEX_CONFIG_DATA
CA response for Configuration
transaction that originates from
PEX_CONFIG_ADDR/
PEX_CONFIG_DATA
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Error Type
Table 17-126. Error Conditions
Log error (PEX_ERR_DR[PCT]) and send interrupt to PIC, if enabled.
Log unexpected completion error (PCI Express Uncorrectable Status
Register[16]) and send interrupt to PIC, if enabled.
Depending upon whether the initial internal request was broken up, the
error is not sent until all responses come back for all portions of the
internal request.
Log the error (PEX_ERR_DR[CDNSC] and PCI Express
Uncorrectable Status Register[20]) and send interrupt to PIC, if
enabled.
Depending upon whether the initial internal request was broken up, the
error is not sent until all responses come back for all portions of the
internal request.
Log the error (PEX_ERR_DR[PCAC, CDNSC] and PCI Express
Uncorrectable Status Register[15] and send interrupt to PIC, if
enabled.
Depending upon whether the initial internal request was broken up, the
error is not sent until all responses come back for all portions of the
internal request.
Log the error (PCI Express Uncorrectable Status Register[12]) and
send interrupt to PIC, if enabled.
Depending upon whether the initial internal request was broken up, the
error is not sent until all responses come back for all portions of the
internal request.
Log the error (PCI Express Uncorrectable Status Register[19]) and
send interrupt to PIC, if enabled.
1.The controller always retries the transaction as soon as possible until
a status other than CRS is returned. However, if a CRS status is
returned after the configuration retry timeout (PEXCONF_RTY_TOR)
timer expires, then the controller aborts the transaction and sends all
1s (0xFFFF_FFFF) data back to requester.
2. Log the error (PEX_ERR_DR[PCT]) and send interrupt to the PIC, if
enabled.
1. Send back all 1s (0xFFFF_FFFF) data.
2. Log the error (PEX_ERR_DR[CDNSC] and PCI Express
Uncorrectable Status Register[20]) and send interrupt to PIC, if
enabled.
1. Send back all 1s (0xFFFF_FFFF) data.
2. Log the error (PEX_ERR_DR[PCAC, CDNSC] and PCI Express
Uncorrectable Status Register[15]) and send interrupt to PIC, if
enabled.
Action
PCI Express Interface Controller
17-111