MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1470

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.8.3.6.2
21.8.4
The device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device
Transfer Descriptor (dTD). An area of memory pointed to by ENDPOINTLISTADDR contains a group of
all dQH's in a sequential list as shown in
receive endpoints (OUT/SETUP) and the odd elements are used for transmit endpoints (IN/INTERRUPT).
Device transfer descriptors are linked head to tail starting at the queue head and ending at a terminate bit.
Once the dTD has been retired, it will no longer be part of the linked list from the queue head. Therefore,
21-136
ENDPOINTLISTADDR
32 Elements
Managing Queue Heads
1
2
Priming an endpoint towards the end of (micro)frame N-1 will not guarantee
delivery in (micro)frame N. The delivery may actually occur in
(micro)frame N+1 if device controller does not have enough time to
complete the prime before the SOF for packet N is received.
Isochronous Endpoint Bus Response Matrix
Zero Length Packet.
Force Bit Stuff Error.
Up to
Invalid
Setup
Ping
Out
In
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-89. Isochronous Endpoint Bus Response Matrix
NULL
STALL
Ignore
Ignore
Ignore
Endpoint QH 0—Out
Endpoint QH 1—Out
Stall
Endpoint QH 0—In
Figure 21-63. Endpoint Queue Head Diagram
1
Packet
Endpoint Queue Heads
•
•
•
NULL Packet
Figure
Not Primed
STALL
Ignore
Ignore
Ignore
CAUTION
21-63. The even elements in the list of dQH's are used for
Transmit
Receive
Primed
STALL
Ignore
Ignore
Transfer
Pointer
Buffer
Transfer Buffer Pointer
Endpoint Transfer Descriptor
Transfer Buffer Pointer
Underflow
BS Error
Ignore
Ignore
N/A
N/A
Transfer
Buffer
2
Drop Packet
Transfer
Buffer
Overflow
Transfer Buffer Pointer
Ignore
Ignore
N/A
N/A
Freescale Semiconductor
Transfer
Transfer
Buffer
Buffer