MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 826

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.5.3
The IPGIFG register is written by the user.
Table 14-45
14-78
Offset eTSEC1:0x2_4508;
Reset 0
16–23
25–31
9–15
Bits
1–7
24
0
8
W
R
eTSEC3:0x2_6508
—
0
Inter-Packet-Gap, Part 1
Inter-Packet-Gap, Part 2
Inter-Packet-Gap, Part 1
1
1
Non-Back-to-Back
Non-Back-to-Back
Inter-Packet-Gap
Non-Back-to-Back
describes the fields of the IPGIFG register.
Minimum IFG
Back-to-Back
0
Enforcement
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)
Name
0
—
—
—
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
0
7
Reserved
This is a programmable field representing the optional carrier sense window referenced in
IEEE 802.3/4.2.3.2.1 ‘carrier deference’. If carrier is detected during the timing of IPGR1,
the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC
continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which
follows the two-thirds/one-third guideline.
Reserved
This is a programmable field representing the non-back-to-back inter-packet-gap in bits. Its
default is 0x60 (96d), which represents the minimum IPG of 96 bits.
This is a programmable field representing the minimum number of bits of IFG to enforce
between frames. A frame is dropped whose IFG is less than that programmed. The default
setting of 0x50 (80d) represents half of the nominal minimum IFG which is 160 bits.
Reserved
This is a programmable field representing the IPG between back-to-back packets. This is
the IPG parameter used exclusively in full-duplex mode and in half-duplex mode if two
transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired.
The default setting of 0x60 (96d) represents the minimum IPG of 96 bits.
—
0
8
Figure 14-41. IPGIFG Register Definition
Table 14-45. IPGIFG Field Descriptions
Inter-Packet-Gap, Part 2
1
9
Non-Back-to-Back
1
0
Figure 14-41
0
0
0
15 16
0
0
describes the definition for IPGIFG.
1
Minimum IFG
Description
Enforcement
0
1
0
0
0
23 24 25
0
—
0
Freescale Semiconductor
1
Inter-Packet-Gap
1
Access: Read/Write
Back-to-Back
0
0
0
0
31
0