MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1603

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25-20
25.3.2.7
The trace buffer access data high register (TBADHR), shown in
bits of the data read from the trace buffer during a software-initiated read command (TBACR[RD]), or the
write data to be written into the trace buffer during a software-initiated write command (TBACR[WR]).
TBACR must be configured to perform a read before this register contains valid data. This register must
be initialized by software before configuring the TBACR to perform a write command.
Table 25-21
25.3.2.8
The trace buffer access data register (TBADR), shown in
the data read from the trace buffer during a software-initiated read command (TBACR[RD]) or the write
data to be written into the trace buffer during a software-initiated write command (TBACR[WR]). TBACR
Freescale Semiconductor
0–31
24–31
Bits
2–23
Bits
Offset 0x064
Reset
0
1
W
R
TBADH Trace buffer access data high. The higher 32 bits of the data read from or to be written into the trace buffer,
Name
0
Name
INDX
WR
RD
—
describes the TBACR fields.
describes TBADHR.
Trace Buffer Access Data High Register (TBADHR)
Trace Buffer Access Data Register (TBADR)
depending on whether the array is accessed with a read or a write.
Read command. When set, a trace buffer read is performed using the value of TBACR[INDX]. This bit is
automatically cleared when the read is performed.
Write command. When set, a trace buffer write is performed using the value of TBACR[INDX]. This bit is
automatically cleared when the write is performed. A write occurs only if the trace buffer is not active: write
requests are ignored while the buffer is active.
Reserved
Buffer index to read from or write into (0–255). Used in conjunction with TBACR[RD] and TBACR[WR].
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 25-15. Trace Buffer Read High Register (TBADHR)
Table 25-21. TBADHR Field Descriptions
Table 25-20. TBACR Field Descriptions
All zeros
TBADH
Description
Description
Figure
Figure
25-16, contains the low-order 32 bits of
25-15, contains the high-order 32
Debug Features and Watchpoint Facility
Access: Read/Write
31
25-21