MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 19

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
11.4.4.2.1
11.4.4.2.2
11.4.4.3
11.4.5
11.4.5.1
11.4.5.2
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.7.1
11.5.7.2
11.5.8
12.1
12.1.1
12.1.2
12.2
12.3
12.3.1
12.3.1.1
12.3.1.2
12.3.1.3
12.3.1.4
12.3.1.5
12.3.1.6
12.3.1.7
12.3.1.8
12.3.1.9
12.3.1.10
12.3.1.11
12.3.1.12
12.3.1.13
Freescale Semiconductor
Initialization/Application Information ......................................................................... 11-21
Overview........................................................................................................................ 12-1
External Signal Descriptions ......................................................................................... 12-3
Memory Map/Register Definition ................................................................................. 12-3
Boot Sequencer Mode.............................................................................................. 11-17
Initialization Sequence............................................................................................. 11-21
Generation of START .............................................................................................. 11-21
Post-Transfer Software Response ............................................................................ 11-22
Generation of STOP................................................................................................. 11-22
Generation of Repeated START .............................................................................. 11-23
Generation of SCL When SDA Low ....................................................................... 11-23
Slave Mode Interrupt Service Routine..................................................................... 11-23
Interrupt Service Routine Flowchart........................................................................ 11-24
Features...................................................................................................................... 12-1
Modes of Operation ................................................................................................... 12-2
Register Descriptions................................................................................................. 12-5
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Clock Stretching .................................................................................................. 11-17
EEPROM Calling Address .................................................................................. 11-18
EEPROM Data Format ........................................................................................ 11-19
Slave Transmitter and Received Acknowledge ................................................... 11-23
Loss of Arbitration and Forcing of Slave Mode.................................................. 11-24
Receiver Buffer Registers (URBRn) (ULCR[DLAB] = 0) ................................... 12-5
Transmitter Holding Registers (UTHRn) (ULCR[DLAB] = 0) ............................ 12-5
Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 12-7
Interrupt ID Registers (UIIRn) (ULCR[DLAB] = 0) ............................................ 12-8
FIFO Control Registers (UFCRn) (ULCR[DLAB] = 0) ..................................... 12-10
Alternate Function Registers (UAFRn) (ULCR[DLAB] = 1) ............................. 12-11
Line Control Registers (ULCRn)......................................................................... 12-11
Modem Control Registers (UMCRn) .................................................................. 12-14
Line Status Registers (ULSRn) ........................................................................... 12-15
Modem Status Registers (UMSRn) ..................................................................... 12-16
Scratch Registers (USCRn) ................................................................................. 12-17
DMA Status Registers (UDSRn) ......................................................................... 12-17
Input Signal Synchronization .......................................................................... 11-16
Filtering of SCL and SDA Lines ..................................................................... 11-17
(ULCR[DLAB] = 1) .......................................................................................... 12-6
Contents
Chapter 12
DUART
Title
Number
Page
xix