MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 8

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.1.1
6.9.1.2
6.9.2
6.9.3
6.9.3.1
6.9.3.2
6.9.4
6.9.5
6.9.6
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.4
7.2.1.5
7.2.1.6
7.2.1.7
7.2.1.8
viii
L2 Cache Locking.......................................................................................................... 6-29
PLRU L2 Replacement Policy....................................................................................... 6-31
L2 Cache Operation ....................................................................................................... 6-33
Introduction...................................................................................................................... 7-1
Memory Map/Register Definition ................................................................................... 7-3
Locking the Entire L2 Cache ..................................................................................... 6-29
Locking Programmed Memory Ranges..................................................................... 6-30
Locking Selected Lines.............................................................................................. 6-30
Clearing Locks on Selected Lines ............................................................................. 6-30
Flash Clearing of Instruction and Data Locks ........................................................... 6-31
Locks with Stale Data ................................................................................................ 6-31
PLRU Bit Update Considerations.............................................................................. 6-32
Allocation of Lines .................................................................................................... 6-32
Initialization ............................................................................................................... 6-33
Flash Invalidation of the L2 Cache............................................................................ 6-34
Managing Errors ........................................................................................................ 6-34
L2 Cache States ......................................................................................................... 6-34
L2 State Transitions ................................................................................................... 6-35
Error Checking and Correcting (ECC) ...................................................................... 6-39
Overview...................................................................................................................... 7-2
Features........................................................................................................................ 7-2
Register Descriptions................................................................................................... 7-3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
L2 Cache Initialization .......................................................................................... 6-33
Memory-Mapped SRAM Initialization ................................................................. 6-33
ECC Errors............................................................................................................. 6-34
Tag Parity Errors.................................................................................................... 6-34
ECM CCB Address Configuration Register (EEBACR) ........................................ 7-3
ECM CCB Port Configuration Register (EEBPCR) ............................................... 7-4
ECM IP Block Revision Register 1 (EIPBRR1) ..................................................... 7-5
ECM IP Block Revision Register 2 (EIPBRR2) ..................................................... 7-5
ECM Error Detect Register (EEDR) ....................................................................... 7-6
ECM Error Enable Register (EEER) ....................................................................... 7-7
ECM Error Attributes Capture Register (EEATR) .................................................. 7-7
ECM Error Low Address Capture Register (EELADR) ......................................... 7-8
Memory, Security, and I/O Interfaces
e500 Coherency Module
Contents
Chapter 7
Part III
Title
Freescale Semiconductor
Number
Page