MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 540

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.4.2
This value indicates the number of bytes of key memory that should be used in encrypting or decrypting.
If the DEU mode register is set for single DES, any value other than 8 bytes automatically generates a key
size error in the DEU interrupt status register. If the mode bit is set for triple DES, any value other than 16
bytes (112 bits for 2-key triple DES (K1=K3) or 24 bytes (168 bits for 3-key triple DES) generates an error.
Triple DES always uses K1 to encrypt, K2 to decrypt, K3 to encrypt.
Table 10-48
10.7.4.3
The DEUDSR, shown in
divisible by the DES algorithm block size of 64 bits. The DEU does not automatically pad messages out
to 64-bit blocks; therefore, any message processed by the DEU must be divisible by 64 bits or a data size
error will occur.
In channel-driven operation, the full message length (data size) to be encrypted or decrypted by the DEU
is copied from the descriptor to the DEUDSR; however, only bits 58–63 are checked to determine if there
is a data size error. If bits 58–63 are all zeros, the message is evenly divisible into 64-bit blocks. In
host-driven operation,the user must write the data size to the DEUDSR. If bits 58–63 are not all zero, then
a data size error occurs.This register is cleared when the DEU is reset or re-initialized.
10-110
Offset 0x3_2008
Reset
W
R
52–63
0–51
Bits
0
shows the legal values for DEU key size.
DEU Key Size Register
DEU Data Size Register (DEUDSR)
Key Size
Name
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
Table 10-48. DEU Key Size Register Field Descriptions
Reserved
8 bytes = 0x08 (only legal value if mode is single DES.)
16 bytes = 0x10 (for 2 key 3DES, K1 = K3)
24 bytes = 0x18 (for 3 key 3DES)
Table 10-47. DEU Cipher Modes (continued)
10-58, is used to verify that the data to be processed by the DEU is
Figure 10-57. DEU Key Size Register
—
CFB-64
OFB-64
Mode
All zeros
Description
CM (60:61)
10
11
51 52
Freescale Semiconductor
Key Size
Access: Read/Write
63