MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 591

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.8.8
RNGU allows the user to input entropy bits into the PRNG algorithm to modify the randomness of the
RNGU. This group of registers are write-only, and all writes to these registers are ignored when the RNGU
is busy. However when the RNGU is idle (FIFO is full or RNGU has not yet been started), all data written
to these registers is used to modify the internal XKEY structure. These 64-bit registers cannot be written
back-to-back—there must be a clock cycle in between writes, since the RNGU only processes 32 bits per
cycle.
10.7.8.9
RNGU uses an output FIFO to collect periodically sampled random 64-bit-words, with the intent that
random data always be available for reading. Normally, the channels control all access to this FIFO. For
host-controlled operation, a read from anywhere in the RNGU FIFO address space dequeues data from the
RNGU output FIFO.
The output FIFO is readable by byte, word, or dword. When all 8 bytes of the head dword have been read,
that dword is automatically dequeued from the FIFO so that the next dword (if any) becomes available for
reading. If any byte is read twice between dequeues, it causes an error interrupt of type AE from the EU.
Underflows caused by reading or writing the RNGU output FIFO are reflected in the RNGU interrupt
status register. Also, a write to the RNGU output FIFO space is reflected as an addressing error in the
RNGU interrupt status register.
Freescale Semiconductor
RNGU Entropy Registers
RNGU FIFO
Host reads of the RNGB FIFO should be performed on an 8-byte basis,
regardless of how many bits of random number is actually required. Partial
host reads can leave the RNGB FIFO in a state that results in a channel error.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Security Engine (SEC) 3.0
10-161