MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 509

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operation of the AESU in GCM cipher mode requires the following steps (note these steps are performed
automatically in channel-driven access):
Freescale Semiconductor
1. Reset.
2. Set cipher mode to GCM or GCM with ICV and specify encrypt, decrypt in the AESU mode
3. Load key
4. Load (restore) context as needed (see
5. Set key size
6. Set the size of the computed/received MAC (8, 12 or 16 bytes, default is 16)
7. Set data size
8. While available:
9. Write to the end of message register
10. Unload final ciphertext (for encryption) or plaintext (for decryption) blocks
11. Read (Save) context registers if another segment of the message is processed later
12. Read final GCM MAC from context registers 1-2, if AUX2 bit was set in mode register
13. For GCM with ICV, check ICCR bits in the AESU status register
a.
b.
c.
d.
register. To perform GCM-GHASH (only GHASH (H, AAD, ciphertext) is computed) set AUX0
and specify encrypt. Set AUX2 and AUX1 bits according to
Load IV into the input FIFO (1 or multiple blocks up to 2
Load AAD into the input FIFO (0 or multiple blocks up to 2
Load plaintext (for encryption) or ciphertext (for decryption) blocks into the input FIFO
Unload ciphertext (for encryption) or plaintext (for decryption) blocks from the output FIFO
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-33
to
Table 10-36
Table 10-32
64
bits in total)
64
bits in total)
).
.
Security Engine (SEC) 3.0
10-79