MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 330

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.38
The memory error disable register, shown in
controller’s error detection circuitry. Disabled errors are not detected or reported.
Table 8-44
8-56
25–27
Offset 0xE44
Reset
0–22
Bits
23
24
28
29
30
31
W
R
0
MBED Multiple-bit ECC error disable
MSED Memory select error disable
Name
APED Address parity error disable
ACED Automatic calibration error disable
SBED Single-bit ECC error disable
—
—
—
describes the ERR_DISABLE fields.
Memory Error Disable (ERR_DISABLE)
Reserved
0 Address parity errors are detected if DDR_SDRAM_CFG_2[AP_EN] is set. They are reported if
1 Address parity errors are not detected or reported.
0 Automatic calibration errors are enabled.
1 Automatic calibration errors are disabled.
Reserved
0 Multiple-bit ECC errors are detected if DDR_SDRAM_CFG[ECC_EN] is set. They are reported if
1 Multiple-bit ECC errors are not detected or reported.
0 Single-bit ECC errors are enabled.
1 Single-bit ECC errors are disabled.
Reserved
0 Memory select errors are enabled.
1 Memory select errors are disabled.
ERR_INT_EN[APEE] is set.
ERR_INT_EN[MBEE] is set. Note that uncorrectable read errors cause the assertion of core_fault_in ,
which causes the core to generate a machine check interrupt, unless it is disabled (by clearing
HID1[RFXE]). If RFXE is zero and this error occurs, MBED and ERR_INT_EN[MBEE] must be zero and
ECC_EN must be one to ensure that an interrupt is generated.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-39. Memory Error Disable Register (ERR_DISABLE)
Table 8-44. ERR_DISABLE Field Descriptions
—
Figure
All zeros
8-39, allows selective disabling of the DDR
Description
22
APED ACED
23
24
25
—
27
MBED SBED — MSED
Freescale Semiconductor
28
Access: Read/Write
29
30
31