MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 227

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.3
The e500 core connects to the L2 cache and the system interface through the high-speed core complex bus
(CCB). The e500 core and the L2 cache connect to the rest of the integrated device through the e500
coherency module (ECM).
e500 core can simultaneously read 128 bits of data from the L2/SRAM, read 64 bits of data from the
system interface, and write 128 bits of data to the L2/SRAM and/or system interface.
Freescale Semiconductor
(single 256-KB SRAM if L2SIZ=512 KB)
(single 128-KB SRAM if L2SIZ=512 KB)
(single 128-KB SRAM if L2SIZ=512 KB)
(single 64-KB SRAM if L2SIZ=512 KB)
(single 64-KB SRAM if L2SIZ=512 KB)
(two 256-KB SRAM if L2SIZ=512 KB)
Two quarters of the array are SRAMs
One eighth of the array is an SRAM
Two eighths of the array are SRAM
One quarter of the array is SRAM
Both halves of array are SRAM
One half of array is an SRAM
Description
Connection of the On-Chip Memory to the System
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 6-2. Way Selection for SRAM Accesses (continued)
Figure 6-5
L2SRAM
shows the data connections of the e500 core and L2/SRAM. The
010
011
100
101
110
111
BAR 0 Hit
1
1
0
1
1
0
1
1
0
BAR 1 Hit
0
0
1
0
0
1
0
0
1
Addr[17–19]
L2 Look-Aside Cache/SRAM
x00
x01
x10
x11
x00
x01
x10
x11
x00
x01
x10
x11
xx0
xx1
xx0
xx1
xx0
xx1
—
—
—
Way Select
0
1
2
3
0
1
2
3
4
5
6
7
0
1
0
1
2
3
0
0
1
6-7