MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1505

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.1.6
Shown in
Reference Clock
Table 23-9
23.4.1.7
GPPORCR stores the value sampled from the local bus address/data signals, LAD[0:31], during POR, as
described in
inform the operating system about initial system configuration. Typical interpretations include circuit
board type, board ID number, or a list of available peripherals.
GPPORCR is shown in
Freescale Semiconductor
Offset 0x014
Reset n 0 0 0 n n n n 0 0 0 0 0 0 0 0 0 0
18–19 SRDS2_REFCLK SerDes2 reference clock
21–31
0–17
Bits
Offset 0x020
Reset n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
W
R
W
R
0
0
Figure
describes the bit settings of PORDEVSR2.
Name
Section 4.4.3.24, “General-Purpose POR Configuration.”
POR Device Status Register 2 (PORDEVSR2)
General-Purpose POR Configuration Register (GPPORCR)
—
—
23-6,the PORDEVSR2 reports POR settings as described in
Configuration.”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
00 Reserved
01 When configured for SATA: SerDes2 expects a 150 MHz reference clock frequency. This should
10 SerDes2 expects a 125 MHz reference clock frequency for either SATA or SGMII functionality.
11 SerDes2 expects a 100 MHz reference clock frequency for either SATA or SGMII functionality.
Reserved
Figure
Figure 23-6. POR Device Status Register 2 (PORDEVSR2)
POR_CFG_VEC
Figure 23-7. POR Configuration Register (GPPORCR)
not be used when SerDes2 is configured for SGMII.
(default).
—
Table 23-9. PORDEVSR2 Field Descriptions
23-7.
17
SRDS2_REFCLK
Description
18
0
19
0
Software can use this value to
POR_CFG_VEC
20
0 0 0 0 0 0 0 1 1 1 1 1
Section 4.4.3.13, “Serdes 2
Access: Read Only
—
Access: Read only
Global Utilities
31
23-13
31