MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 239

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-11
Figure 6-15
Table 6-12
Freescale Semiconductor
Offset 0x2_0E08
Reset
16–21
24–31
0–31
0–14
Bits
Bits
15
22
23
W
R
0
EIMASKLO Error injection mask/low word. A set bit corresponding to a data path bit causes that bit on the data path
ECCERRIM Error injection mask for the ECC bits. A set bit corresponding to an ECC bit causes that bit to be
DERRIEN
TERRIEN
ECCMB
describes L2ERRINJLO[EIMASKLO].
Name
describes L2ERRINJCTL fields.
Name
shows the L2 error injection mask control register (L2ERRINJCTL).
—
—
Figure 6-15. L2 Error Injection Mask Control Register (L2ERRINJCTL)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
to be inverted on SRAM writes if L2ERRINJCTL[DERRIEN] = 1.
Reserved
0 No tag errors are injected.
1 All subsequent entries written to the L2 tag array have the parity bit inverted.
Reserved
0 ECC byte mirroring is disabled
1 The most significant data path byte is mirrored onto the ECC byte if DERRIEN = 1.
0 No data errors are injected.
1 Subsequent entries written to the L2 data array have data or ECC bits inverted as specified in the
Note: if both ECC mirror byte and data error injection are enabled, ECC mask error injection is
performed on the mirrored ECC.
inverted on SRAM writes if DERRIEN = 1.
L2 tag array error injection enable
ECC mirror byte enable.
L2 data array error injection enable:
—
data and ECC error injection masks and/or data path byte mirrored onto ECC as specified by ECC
mirror byte enable.
Table 6-12. L2ERRINJCTL Field Descriptions
Table 6-11. L2ERRINJLO Field Description
14
TERRIEN
15
16
All zeros
—
Description
Description
21
ECCMB
22
DERRIEN
23
L2 Look-Aside Cache/SRAM
24
Access: Read/Write
ECCERRIM
6-19
31