MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1575

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC total interrupt count
PIC interrupt wait cycles
PIC interrupt service cycles
PIC interrupt select 0 (duration
threshold)
PIC interrupt select 1 (duration
threshold)
PIC interrupt select 2 (duration
threshold)
PIC interrupt select 3 (duration
threshold)
PCI clock cycles
PCI inbound memory reads
PCI inbound memory writes
PCI inbound config reads
PCI inbound config writes
PCI outbound memory reads
PCI outbound memory writes
PCI outbound I/O reads
PCI outbound I/O writes
PCI outbound config reads
PCI outbound config writes
PCI inbound 32-bit read data beats
PCI inbound 32-bit write data beats
PCI outbound 32-bit read data beats
PCI outbound 32-bit write data beats
PCI total transactions
PCI inbound purgeable reads
PCI inbound (speculative reads)
purgeable reads discarded
PCI idle cycles
PCI dual address cycles
PCI internal cycles
Freescale Semiconductor
Event Counted
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 24-10. Performance Monitor Events (continued)
Number
Interrupt Controller (PIC) Events
C8:126
C1:120
C3:123
C5:119
C6:124
C1:126
C2:101
C3:127
C4:101
C3:101
C4:102
C2:102
C3:102
C4:103
C8:127
C2:104
C3:103
Ref:26
Ref:28
C2:83
C5:94
C6:96
C7:90
C8:90
C1:94
C7:93
C2:66
C1:95
PCI Events
Total number of interrupts serviced
Counts cycles when an interrupt waits to be acknowledge
Number of cycles there is an interrupt currently being serviced.
THRESHOLD: select 0–3: interrupt count over threshold. (Note:
only unmasked, nonzero priority requests are acknowledged). The
four interrupts are selected through register pairs,
PM0MR n –PM3MR n . See
Mask Registers (PMMRs).”
—
Includes all read types.
—
—
—
Includes all read types.
Number of PCI outbound memory writes
—
—
Number of PCI outbound config reads
—
—
—
—
—
Includes 32- and 64-bit transactions.
—
—
—
—
—
Description of Event Counted
Section 9.3.4, “Performance Monitor
Device Performance Monitor
24-21