MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1048

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
Table 16-14
16-22
12–15 RTT Read transaction type. Transaction type to run if access is a read. The field description differs subject to
16–19 WTT Write transaction type. Transaction type to run if access is a write. The field description differs subject to
8–11 TRGT 0000 Reserved
Bits Name
3–7
0
1
2
EN
PF
—
—
describes the fields of the PIWARn registers.
Enable. Enables this address translation
Reserved
Prefetchable. Indicates that the address space is prefetchable so that prefetching and streaming are
attempted.
0 Not prefetchable
1 Prefetchable
Reserved
0001 PCI Express 2
0010 PCI Express 1
0011 PCI Express 3
0100–1110 Reserved
1111 Local memory space
the transaction being targeted to I/O interface or to local memory.
Following are the transaction type settings for reads to an I/O interface:
0000–0011 Reserved
0100
0101–1111 Reserved
Following are the transaction type settings for reads to local memory:
0000–0011 Reserved
0100
0101
0110
0111
1000–1111 Reserved
the transaction being targeted to an I/O interface or to local memory.
Following are the transaction type settings for writes to an I/O interface:
0000–0011 Reserved
0100 Write
0101–1111 Reserved
Following are the transaction type settings for writes to local memory:
0000–Reserved
0100 Write, don’t snoop local processor
0101 Write, snoop local processor
0110 Write, allocate L2 cache line
0111 Write, allocate and lock L2 cache line
1000–1111 Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Read
Read, don’t snoop local processor
Read, snoop local processor
Reserved
Read, unlock L2 cache line
Table 16-14. PIWAR n Field Descriptions
Description
Freescale Semiconductor