MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 569

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-64
10.7.6.8
The interrupt status register indicates which unmasked errors have occurred and have generated error
interrupts to the channel. Each bit in this register can only be set if the corresponding bit of the MDEU
interrupt mask register is zero (see
If the MDEU interrupt status register is non-zero, the MDEU halts and the MDEU error interrupt signal is
asserted to the controller (see
MDEU is being operated through channel-controlled access, then an interrupt signal is generated to the
channel to which this EU is assigned. The EU error then appears in bit 55 of the Channel Status Register
(see
If the interrupt status register is written from the host, 1s in the value written are recorded in the interrupt
status register if the corresponding bit is unmasked in the interrupt mask register. All other bits are cleared.
This register can also be cleared by setting the RI bit of the MDEU reset control register.
Freescale Semiconductor
Table
0–57
59-60
Bits
58
61
62
63
10-15) and generates a channel error interrupt to the controller.
describes MDEU status register fields.
MDEU Interrupt Status Register
Name
HALT
ICCR
RD
—
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-64. MDEU Status Register Field Descriptions
Reserved
Halt. Indicates that the MDEU has halted due to an error.
0 MDEU not halted
1 MDEU halted
Note: Because the error causing the MDEU to stop operating may be masked before
Integrity Check Comparison Result
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Note: A “passed” or “failed” result is generated only if ICV checking is enabled.
Error interrupt: This status bit reflects the state of the error interrupt signal, as sampled by
the controller interrupt status register
(ISR)”).
0 MDEU is not signaling error
1 MDEU is signaling error
Done interrupt: This status bit reflects the state of the done interrupt signal, as sampled by
the Controller interrupt status register
(ISR)”).
0 MDEU is not signaling done
1 MDEU is signaling done
Reset Done. This status bit, when high, indicates that MDEU has completed its reset
sequence, as reflected in the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the
Section 10.5.4.2.2, “Interrupt Status Register
reaching the interrupt status register, the MDEU interrupt status register is used to
provide a second source of information regarding errors preventing normal
operation.
register, indicating the EU is ready for operation.
Section 10.7.6.9, “MDEU Interrupt Mask
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
Description
(ISR)”). In addition, if the
Register”).
Security Engine (SEC) 3.0
10-139