MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 892

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.4.3.9
Annex 36A in IEEE 802.3z describes several jitter test patterns. These can be configured to be sent by
writing the jitter diagnostics register. See the register description for more information. In may be wise to
auto-negotiate and advertise a remote fault signaling of offline prior to beginning the test patterns.
Figure 14-130
Table 14-140
14-144
6–15
Bits
1–3
4–5
0
Offset 0x10
Reset
Custom Jitter
Jitter Enable Jitter enable. This bit is cleared by default.
Jitter Select
W
R
Pattern
Name
—
Enable
describes the fields of the JD register.
Jitter
describes the definition for the JD register.
Jitter Diagnostics Register (JD)
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 Normal transmit operation.
1 Enable the TBI to transmit the jitter test patterns defined in IEEE 802.3z 36A.
Selects the jitter pattern to be transmitted in diagnostics mode. Encoding of this field is shown in the
following table. Default is 00.
Reserved
Used in conjunction with jitter (pattern) select and jitter (diagnostic) enable; set this field to the desired
custom pattern which is continuously transmitted. Its default is 0x000.
User defined uses custom jitter pattern, bits 6–15
High frequency (+/- D21.5)
1010101010101010101010101010101010101010…
Mixed frequency (+/- K28.5)
1111101011000001010011111010110000010100…
Low frequency
1111100000111110000011111000001111100000…
Complex pattern (10’h17c,10’h0c9,10’h0e5,10’h2a3, 10’h17c,...)
Square Wave (- K28.7)
0011111000001111100000111110000011111000…
Reserved
Reserved
1
Jitter Select
Figure 14-130. Jitter Diagnostics Register Definition
3
Table 14-140. JD Field Descriptions
4
Jitter Pattern Select
—
5
6
All zeros
Description
Custom Jitter Pattern
bit[1]
0
0
0
0
1
1
1
1
Freescale Semiconductor
bit[2]
0
0
1
1
0
0
1
1
Access: Read/Write
bit[3]
0
1
0
1
0
1
0
1
15