MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 489

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
53–55
56–57
Bits
58
59
Finalize MAC for
Use Context for
Use Context for
CCM and GCM
Generate Final
CMAC derived
Initialize CCM
Enable RBP
derived keys
XCBC-MAC
AUX2 =
GHASH
AUX2 =
AUX2 =
AUX1 =
AUX1 =
AUX1 =
AUX1 =
ICV Bit
modes
Name
AUX2
AUX1
ECM
keys
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-22. AESU Mode Register Field Descriptions (continued)
Reserved, must be cleared.
Extended Cipher Mode. Used in combination with bits 61:62 (Cipher Mode) to select the cipher
mode for AES operation. See
AUX2 Mode. Definition depends upon the value of the 4 Cipher Mode (CM) and Extended Cipher
Mode (ECM) bits:
AUX1 Mode. Definition depends upon the value of the 4 Cipher Mode and Extended Cipher Mode
bits:
• CCM and GCM Cipher Modes (ECM=1X, CM=0X): Generate Final MAC Bit—Processes final
• XCBC-MAC and CMAC Cipher Modes (ECM=10, 01, CM=10): ICV Bit—Enables XCBC-MAC
• CBC, CBC-RBP Cipher Modes (ECM=00, CM=01): RBP Bit—Enables CBC-RBP
• CCM Cipher Mode (ECM=10, CM=00): Initialize Mode Bit—Initializes AESU for new message
• GCM Cipher Mode (ECM=10, CM=01): Generate Final GHASH Bit—Enables completion of
• XCBC-MAC Cipher Mode (ECM=10, CM=10): Load Keys—Do not compute K1, K2 and K3, but
• CMAC Cipher Mode (ECM=01, CM=10): Load Keys—Do not compute E(K, 0
message block and generates final MAC tag at the end of message processing.
with ICV and CMAC with ICV Cipher Modes
GHASH computation by signaling that the last iteration of GHASH should be performed. This
last iteration performs XOR of the current (intermediate) GHASH result with the concatenation
of additional authenticated data (AAD) and ciphertext bit lengths in case of GHASH(H, AAD,
ciphertext), or with the concatenation of 0
As an exception, this bit should be cleared if the whole message (IV+AAD+text data) together
with the generation of the final MAC is processed with one descriptor since in that case the
generation of final GHASH is implied. Incidentally, whenever AUX1=1 in GCM cipher mode, the
total bit lengths of AAD, text data or IV must be provided in context registers 9-10.
instead use the keys loaded in the Key Data Registers (K1), and Context Registers 5-6 (K2) and
7-8 (K3).
and K2, but instead use the value loaded in Context Registers 3-4. This is useful after a context
switch. Deriving K1 and K2 does not incur any timing penalty.
0 = Do not generate final MAC tag
1 = Generate final MAC tag after CCM/GCM processing is complete. Note that for GCM,
0 = XCBC-MAC or CMAC cipher mode
1 = XCBC-MAC with ICV or CMAC with ICV cipher mode
0 = CBC cipher mode
1 = CBC-RBP cipher mode
0 = Do not initialize (context is loaded by host)
1 = Initialize new message with nonce/initialization vector
0 = Do not perform the last iteration in GHASH(H, AAD, ciphertext) or GHASH(H, {}, IV)
1 = Generate the final result of GHASH(H, AAD, ciphertext) or GHASH(H, {}, IV)—implies
0 = Compute K1=E(K, 16{01}), K2=E(K, 16{02}), K3=E(K, {03}) and write K1 to Context
1 = Load keys: K1= [Key Data Reg 1-2], K2= [Reg 5-6], K3=[Reg 7-8]
0 = Compute E(K, 0
1 = Load E(K, 0
when message processing is split into multiple descriptors, it must be AUX1=1 when
AUX2=1.
unless the message is processed and the final MAC computed in 1 descriptor.
that the message processing is split into multiple descriptors.
Registers 3-4, K2 to 5-6, and K3 to 7-8.
128
) and preserve it in Context Registers 3-4
128
Table 10-23 on page 10-60
) and write it to Context Registers 3-4
Description
64
and the bit length of IV in case of GHASH(H, {}, IV).
for mode bit combinations.
Security Engine (SEC) 3.0
128
) to derive K1
10-59