MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 212

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Reset, Clocking, and Initialization

This configuration results in a 32-bit byte address with a 0-bit effective page number. Therefore the 36-bit

real address is equal to the 32-bit effective address, with the 4 MSbits of the 36-bit real address equal to 0.

The on-chip ROM code does not setup any Local Access Windows. Access to CCSR address space (and

therefore by extension, also access to the on-chip ROM) doesn’t require a Local Access Window. It is the

user’s responsibility to setup a local access window through a Control Word address/data pair for the

desired Target Address and Execution Starting Address (which will typically be in either DDR or Local

Bus memory space).

Note that any such local access window configured at this time must have the 4 MSbits of the address equal

to 0. This is due to the 32-bit addressing enabled by the e500 MMUs as described above.

The user can reconfigure the system in the user code portion based on system requirements.

UX/UR/UW=000 (No user mode access allowed)

WIMGE=01110 (Cache-inhibited, Memory coherency required, Guarded)

IPROT=1 (Page is protected from invalidation)

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Freescale Semiconductor