MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1475

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a data
buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as
indicated.
21.8.6
The interrupt service routine must consider that there are high-frequency, low-frequency operations, and
error operations and order accordingly.
21.8.6.1
High frequency interrupts in particular should be handed in the order below. The most important of these
is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible.
1
21.8.6.2
The low frequency events include the following interrupts. These interrupt can be handled in any order
since they don't occur often in comparison to the high-frequency interrupts.
Freescale Semiconductor
Overflow
ISO Packet
Error
ISO Fulfillment
Error
Execution
It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service
Routine.
Order
1a
1b
2
USB Interrupt
ENDPTSETUPSTATUS
USB Interrupt
ENDPTCOMPLETE
SOF Interrupt
Servicing Interrupts
High-Frequency Interrupts
Low-Frequency Interrupts
Number of bytes received exceeded max. packet size or total buffer length.
** This error will also set the Halt bit in the dQH and if there are dTDs remaining in the linked list for the
endpoint, then those will not be executed.
CRC Error on received ISO packet. Contents not guaranteed to be correct.
Host failed to complete the number of packets defined in the dQH mult field within the given (micro)frame. For
scheduled data delivery the DCD may need to readjust the data queue because a fulfillment error will cause
Device Controller to cease data transfers on the pipe for one (micro)frame. During the ‘dead’ (micro)frame,
the Device Controller reports error on the pipe and primes for the following frame.
Interrupt
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
Copy contents of setup buffer and acknowledge setup packet (as indicated in section
Managing Queue Heads). Process setup packet according to USB 2.0 Chapter 9 or
application specific protocol.
Handle completion of dTD as indicated in section Managing Queue Heads.
Action as deemed necessary by application. This interrupt may not have a use in all
applications.
Table 21-92. Interrupt Handling Order
Table 21-91. Error Descriptions
Action
Universal Serial Bus Interfaces
21-141