MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 636

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
12-18
DMS
DMS
DMS
Bits
6
7
0
0
1
1
0
0
1
1
0
0
1
1
RXRDY Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends on
TXRDY Transmitter ready. This read-only bit reflects the status of the transmitter FIFO or the UTHR. The status
Name
FEN
FEN
FEN
0
1
0
1
0
1
0
1
0
1
0
1
DMA Mode
DMA Mode
DMA Mode
depends on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.
0 The bit is cleared, as shown in
1 This bit is set, as shown in
the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.
0 The bit is cleared, as shown in
1 This bit is set, as shown in
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
0
1
0
0
0
1
0
0
0
1
TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR.
TXRDY is set when the transmitter FIFO is full.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY
remains clear when the transmitter FIFO is not yet full.
RXRDY is set when there are no characters in the receiver FIFO or URBR.
RXRDY is set when the trigger level has not been reached and there has been no time out.
Table 12-19. UDSR Field Descriptions (continued)
Table 12-21. UDSR[TXRDY] Cleared Conditions
Table 12-22. UDSR[RXRDY] Set Conditions
Table 12-20. UDSR[TXRDY] Set Conditions
Table
Table
Table
Table
12-20.
12-22.
12-21.
12-23.
Description
Meaning
Meaning
Meaning
Freescale Semiconductor