MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1036

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
16-10
PCI_SERR
PCI_STOP
PCI_TRDY
Signal
Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI system error.The PCI system error signal is both an input and output signal on this PCI controller.
I/O Stop.The stop signal is both an input and output signal on this PCI controller.
I/O Target ready. Both an input and output signal on this PCI controller.
O As outputs for the bidirectional PCI system error, these signals operate as described below.
O As outputs for the bidirectional stop, these signals operate as described below.
O As outputs for the bidirectional target ready, these signals operate as described below.
I As inputs for the bidirectional PCI system error, these signals operate as described below.
I As inputs for the bidirectional stop, these signals operate as described below.
I As inputs for the bidirectional target ready, these signals operate as described below.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
State
State
State
State
State
State
Asserted—Indicates that an address parity error, a target-abort (when this PCI controller is
Negated—Indicates no error.
Asserted—Indicates that a target (other than this PCI controller) has detected a
Negated—Indicates no error.
Asserted—Indicates that this PCI controller, acting as a PCI target, is requesting that the
Negated—Indicates that the current transaction can continue.
Asserted—Indicates that a target is requesting that the PCI initiator stop the current
Negated—Indicates that the current transaction can continue.
Asserted—Indicates that this PCI controller, acting as a PCI target, can complete the
Negated—Indicates that the PCI initiator needs to wait before this PCI controller, acting as
Asserted—Another PCI target is able to complete the current data phase of a transaction.
Negated—Indicates a wait cycle from another target.
acting as the initiator), or some other system error (where the result is a catastrophic
error) was detected.
catastrophic error.
initiator stop the current transaction.
transaction.
current data phase of a PCI transaction. During a read, this PCI controller asserts
PCI_TRDY to indicate that valid data is present on the data bus. During a write, this
PCI controller asserts PCI_TRDY to indicate that it is prepared to accept data.
a PCI target, can complete the current data phase. During a read, this PCI controller
negates PCI_TRDY to insert a wait cycle when it cannot provide valid data to the
initiator. During a write, this PCI controller negates PCI_TRDY to insert a wait cycle
when it cannot accept data from the initiator.
Description
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