MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1310

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.4.17 Host Controller Version Register (HOSTVER)
The host controller version register contains the version for the vendor and the host controller. All the bits
are read-only.
20-36
FEVTCNIBAC12E
Reset
FEVTAC12EBE
FEVTAC12TOE
FEVTAC12CE
FEVTAC12NE
Offset: 0x0FC (HOSTVER)
FEVTAC12IE
16–23
24–31
Field
0–15
VVN
SVN
16–23
25–26
Field
W
R
24
27
28
29
30
31
0
0
Reserved
Vendor version number. The host driver should not use this status. The upper and the lower 4-bits indicate the
version.
0x00
0x01
others
Specification version number. Indicates for the host controller specification version. The upper and the lower
4-bits indicate the version.
0x00
0x01
others
0
0
Reserved
Force event command not executed by Auto CMD12 error. Forces AUTOC12ERR[CNIBAC12E] to set.
Reserved
Force event Auto CMD12 index error. Forces AUTOC12ERR[AC12IE] to set.
Force event Auto CMD12 end bit error. Forces AUTOC12ERR[AC12EBE] to set.
Force event Auto CMD12 CRC error. Forces AUTOC12ERR[AC12CE] to set.
Force event Auto CMD12 time out error. Forces AUTOC12ERR[AC12TOE] to set.
Force event Auto CMD12 not executed. Forces AUTOC12ERR[AC12NE] to set.
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale eSDHC version 1.0
Freescale eSDHC version 2.0
Reserved
SD Host Specification Version 1.0
SD Host Specification Version 2.0, supports the test event register.
Reserved
0
Figure 20-19. Host Controller Version Register (HOSTVER)
0
0
Table 20-24. FEVT Field Descriptions (continued)
0
Table 20-25. HOSTVER Field Descriptions
—
0
0
0
0
0
0
0
Description
15 16
0
Description
0
0
0
0
VVN
0
0
0
23 24
0
0
Freescale Semiconductor
0
0
SVN
0
Access: Read
0
0
0
31
1