MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1486

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Purpose I/O (GPIO)
22.2
The following section provides information about GPIO signals.
22.2.1
Table 22-1
22.3
The GPIO has programmable registers that occupy memory-mapped space. Note that reading undefined
portions of the memory map returns all zeros and writing has no effect.
All GPIO registers are 32 bits wide and are located on 32-bit address boundaries.
Table 22-2
22.3.1
The GPIO direction registers (GPDIR), shown in
22-2
GPIO[0:15]
0xC0C
Offset
0xC00
0xC04
0xC08
0xC10
0xC14
Offset 0xC00
Reset
Signal
W
R
Memory Map/Register Definition
0
External Signal Description
provides detailed descriptions of the external GPIO signals.
shows the memory map of GPIO.
Signals Overview
GPIO Direction Register (GPDIR)
GPIO direction register (GPDIR)
GPIO open drain register (GPODR)
GPIO data register (GPDAT)
GPIO interrupt event register (GPIER)
GPIO interrupt mask register (GPIMR)
GPIO external interrupt control register (GPICR)
I/O
I/O General purpose I/O. Each signal can be set individually to act as input or output, according to application
needs.
Meaning
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Timing Assertion/Negation—Inputs can be asserted completely asynchronously.
Table 22-1. IPIC External Signals—Detailed Signal Descriptions
State
Asserted/Negated—Defined per application.
Outputs are asynchronous to any externally visible clock
Figure 22-2. GPIO Direction Register (GPDIR)
Table 22-2. GPIO Register Address Map
Register
Figure
All zeros
D n
22-2, defines the direction of the individual ports.
Description
Access
R/W
R/W
R/W
R/W
R/W
w1c
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
Undefined
Freescale Semiconductor
Access: Read/write
Section/Page
22.3.1/22-2
22.3.2/22-3
22.3.3/22-3
22.3.4/22-4
22.3.5/22-4
22.3.6/22-5
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