MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1401

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the host controller determines that it is time to execute from the asynchronous list, it uses the
operational register ASYNCLISTADDR to access the asynchronous schedule, as shown in
The ASYNCLISTADDR register contains a physical memory pointer to the next queue head. When the
host controller makes a transition to executing the asynchronous schedule, it begins by reading the queue
head referenced by the ASYNCLISTADDR register. Software must set queue head horizontal pointer
T-bits to a zero for queue heads in the asynchronous schedule.
21.6.6
The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame number changes) of
the high-speed bus and the full- and low-speed bus(es) below USB 2.0 hubs be strictly aligned.
Super-imposed on this requirement is that USB 2.0 hubs manage full- and low-speed transactions via a
micro-frame pipeline (see start- (SS) and complete- (CS) splits illustrated in
direct projection of the frame boundary model into the host controller interface schedule architecture
creates tension (complexity for both hardware and software) between the frame boundaries and the
scheduling mechanisms required to service the full- and low-speed transaction translator periodic
pipelines.
The simple projection, as
scheduling on both the beginning and end of a frame. In order to reduce the complexity for hardware and
software, the host controller is required to implement a one micro-frame phase shift for its view of frame
Freescale Semiconductor
Micro-Frame
FS/LS Bus
Numbers
HS Bus
Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
Figure 21-44. Frame Boundary Relationship Between HS Bus and FS/LS Bus
AsyncListAddr
Operational
USBCMD
Registers
USBSTS
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
7
Figure 21-43. General Format of Asynchronous Schedule List
•
•
•
•
•
•
SS
Boundary
Frame
Figure 21-44
0
1
CS
illustrates, introduces frame-boundary wrap conditions for
2
CS
CS
3
H
SS
4
CS
5
CS
6
CS
Figure
Universal Serial Bus Interfaces
7
CS
21-44). A simple,
0
CS
Figure
1
21-43.
21-67