MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 790

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.2.2
This register is read/write-one-to-clear and is written by the eTSEC to convey DMA status information for
each TxBD ring. The halt bit only has meaning for enabled rings. After processing transmit-related
interrupts, software should use TSTAT to restart transmission from rings that may have been affected by
the interrupt condition. In particular, an error condition that prevents eTSEC from continuing transmission
halts DMA from all rings, including the ring that gave rise to the error.
register.
14-42
Offset eTSEC1:0x2_4104;
Reset
Reset
29–30
Bits
31
W
W
R THLT0
R
eTSEC3:0x2_6104
TXF0
w1c
w1c
TXSCHED Transmit ring scheduling algorithm. This field determines which scheme the transmit scheduler uses to
16
0
Name
—
Transmit Status Register (TSTAT)
THLT1
TXF1
w1c
w1c
17
1
arbitrate between the enabled TxBD rings. The scheme chosen also controls how the DMACTRL and
TQUEUE bits are interpreted. Ring polling is supported only by mode 00; the other modes require
software to restart rings with the TSTAT register. TCP/IP offload can be enabled with any scheduling
mode.
00 Single polled ring mode. TxBD ring 0 is the only ring serviced, even if other rings are enabled and
01 Priority scheduling mode. Frames from enabled TxBD rings are serviced in ascending ring index
10 Modified weighted round-robin scheduling mode. Each TxBD ring is polled in sequence for frames
11 Reserved
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
ready. In this scheduler mode, the DMACTRL[WOP] and DMACTRL[TOD] bits control polling and
retry behavior. This mode supports ring polling, and allows fetching of a non-ready TxBD to be retried
twice.
order.
that are ready for transmission. If a non-ready TxBD is fetched from a ring, that ring is removed from
the scheduling pool until software re-enables it. Ready frames are repeatedly transmitted from a
chosen ring until its transmission quota is exhausted. The transmission quota for TxBD ring n is set
to WT n
more data than its quota allows, the excess is deducted from its quota on the next transmission
opportunity, thereby preventing large frames from monopolizing the eTSEC bandwidth.
THLT2
TXF2
w1c
w1c
18
2
Table 14-16. TCTRL Field Descriptions (continued)
64 bytes, where WT n is a weight from the TR03WT/TR47WT registers. If a ring transmits
THLT3
TXF3
w1c
w1c
19
Figure 14-12. TSTAT Register Definition
3
THLT4
TXF4
w1c
w1c
20
4
THLT5
TXF5
w1c
w1c
21
5
All zeros
All zeros
THLT6
TXF6
w1c
w1c
Description
22
6
THLT7
TXF7
w1c
w1c
23
7
Figure 14-12
24
8
describes the TSTAT
Freescale Semiconductor
—
—
Access: w1c
15
31