MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 300

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.9
The DDR SDRAM control configuration register 2, shown in
configuration for the DDR controller.
8-26
Offset 0x114
Reset
Reset
Bits
30
31
W
W
R
R
FRC_SR SR_IE DLL_RST_DIS — DQS_CFG
MEM_HALT
16
0
Name
Figure 8-10. DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)
BI
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)
1
NUM_PR
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-13. DDR_SDRAM_CFG Field Descriptions (continued)
data read/write transactions to DDR SDRAM until the bit is cleared again. This can be used when
bypassing initialization and forcing MODE REGISTER SET commands through software.
0 DDR controller accepts new transactions.
1 DDR controller finishes any remaining transactions, and then it remains halted until this bit is
Bypass initialization
0 DDR controller cycles through initialization routine based on SDRAM_TYPE
1 Initialization routine is bypassed. Software is responsible for initializing memory through
See
errors in this mode.
DDR memory controller halt. When this bit is set, the memory controller does not accept any new
cleared by software.
DDR_SDRAM_MODE2 register. If software is initializing memory, then the MEM_HALT bit can be
set to prevent the DDR controller from issuing transactions during the initialization sequence.
Note that the DDR controller does not issue a DLL reset to the DRAMs when bypassing the
initialization routine, regardless of the value of DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL
reset is required, then the controller should be forced to enter and exit self refresh after the
controller is enabled.
Section 8.4.1.16, “DDR Initialization Address (DDR_INIT_ADDR),”
2
19
3
20
4
5
6
—
All zeros
All zeros
—
24
8
Description
Figure
OBC_CFG AP_EN D_INIT —
ODT_CFG
25
9
8-10, provides more control
10
26
11
27
for details on avoiding ECC
Freescale Semiconductor
28
Access: Read/Write
RCW
_EN
—
29
—
30
MD_
EN
15
31