MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 167

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
When a system reset is recognized (HRESET is asserted), the MPC8536E aborts all current internal and
external transactions and releases all bidirectional I/O signals to a high-impedance state. See
“Reset, Clocking, and Initialization,”
During reset, the MPC8536E ignores most input signals (except for reset configuration signals) and drives
most output-only signals to an inactive state.
that are not multiplexed with other inputs or are not used as reset configuration signals during system
reset).
Freescale Semiconductor
Functional Interface
Output Signal States During Reset
Debug
USB1
USB2
eLBC
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DDR Memory
DDR Memory
DDR Memory
DDR Memory
DDR Memory
Interface
Table 3-3. MPC8536E Reset Configuration Signals (continued)
Table 3-4. Output Signal States During System Reset
LAD[0:31]
LA27
LA[28:31]
LWE0/LBS0/LFWE
LWE[1:3]/LBS[1:3]
LBCTL
LALE
LGPL0/LFCLE
LGPL1/LFALE
LGPL2/LOE/LFRE
LGPL3/ LFWP
LGPL5
MSRCID0
MSRCID1
USB1_STP
USB2_STP
Functional Signal Name
for a complete description of the reset functionality.
Table 3-4
MPAR_OUT
MBA[2:0]
MCK[0:5]
MA[15:0]
Signal
MCAS
shows the states of the output-only signals (signals
Reset Configuration
cfg_gpinput[0:31]
cfg_host_agt[0:2]
cfg_mem_debug
cfg_core_speed
cfg_sys_pll[0:3]
cfg_sys_speed
cfg_ddr_debug
cfg_dram_type
cfg_boot_seq0
cfg_boot_seq1
cfg_pci_speed
cfg_cpu_boot
cfg_core_pll0
cfg_core_pll1
cfg_core_pll2
cfg_pci_clk
Name
State During Reset
Driven Low
High-Z
High-Z
High-Z
High-Z
Indeterminate if not
driven (no default)
Must be driven
Must be driven
Must be driven
Must be driven
Default
111
1
1
1
1
1
1
1
1
1
1
Signal Descriptions
Chapter 4,
3-17