MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 30

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
15.2
15.2.1
15.2.2
15.3
15.3.1
15.3.1.1
15.3.1.2
15.3.1.3
15.3.1.4
15.3.1.5
15.3.1.6
15.3.1.7
15.3.1.8
15.3.1.9
15.3.1.10
15.3.1.11
15.3.1.12
15.3.1.13
15.3.1.14
15.4
15.4.1
15.4.1.1
15.4.1.1.1
15.4.1.1.2
15.4.1.1.3
15.4.1.1.4
15.4.1.2
15.4.1.2.1
15.4.1.2.2
15.4.1.2.3
15.4.1.2.4
15.4.1.3
15.4.1.4
15.4.1.4.1
15.4.1.4.2
15.4.1.5
15.4.1.6
15.4.1.7
15.4.1.8
15.4.2
15.4.3
xxx
External Signal Description ........................................................................................... 15-4
Memory Map/Register Definition ................................................................................. 15-5
Functional Description................................................................................................. 15-24
Signal Overview ........................................................................................................ 15-4
Detailed Signal Descriptions ..................................................................................... 15-5
DMA Register Descriptions....................................................................................... 15-8
DMA Channel Operation......................................................................................... 15-24
DMA Transfer Interfaces ......................................................................................... 15-32
DMA Errors ............................................................................................................. 15-32
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Mode Registers (MRn) .......................................................................................... 15-9
Status Registers (SRn) ......................................................................................... 15-11
Current Link Descriptor Address Registers (CLNDARn and ECLNDARn) ...... 15-13
Source Attributes Registers (SATRn).................................................................. 15-15
Source Address Registers (SARn)....................................................................... 15-15
Destination Attributes Registers (DATRn).......................................................... 15-16
Destination Address Registers (DARn)............................................................... 15-17
Byte Count Registers (BCRn) ............................................................................. 15-18
Next Link Descriptor Address Registers (NLNDARn and ENLNDARn) .......... 15-18
Current List Descriptor Address Registers (CLSDARn and ECLSDARn)......... 15-19
Next List Descriptor Address Registers (NLSDARn and ENLSDARn)............. 15-21
Source Stride Registers (SSRn) ........................................................................... 15-22
Destination Stride Registers (DSRn) ................................................................... 15-22
DMA General Status Register (DGSR) ............................................................... 15-23
Basic DMA Mode Transfer ................................................................................. 15-25
Extended DMA Mode Transfer ........................................................................... 15-27
External Control Mode Transfer.......................................................................... 15-29
Channel Continue Mode for Cascading Transfer Chains .................................... 15-30
Channel Abort...................................................................................................... 15-31
Bandwidth Control............................................................................................... 15-31
Channel State ....................................................................................................... 15-31
Illustration of Stride Size and Stride Distance..................................................... 15-32
Basic Direct Mode ........................................................................................... 15-25
Basic Direct Single-Write Start Mode ............................................................. 15-26
Basic Chaining Mode ...................................................................................... 15-26
Basic Chaining Single-Write Start Mode ........................................................ 15-27
Extended Direct Mode..................................................................................... 15-27
Extended Direct Single-Write Start Mode....................................................... 15-28
Extended Chaining Mode ................................................................................ 15-28
Extended Chaining Single-Write Start Mode .................................................. 15-28
Basic Mode ...................................................................................................... 15-30
Extended Mode................................................................................................ 15-31
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