MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 311

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.19
The DDR SDRAM timing configuration 5 register, shown in
required to support DDR3 memories.
Freescale Semiconductor
12–15
16–29
30–31
Offset 0x164
8–11
Reset
Bits
W
R
0
DLL_LOCK
—
Name
WWT
RRT
—
DDR SDRAM Timing Configuration 5 (TIMING_CFG_5)
2
Figure 8-20. DDR SDRAM Timing Configuration 5 Register (TIMING_CFG_5)
3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
RODT_ON
Read-to-read turnaround for same chip select. Specifies how many cycles are added between reads
to the same chip select. If a value of 0000 is chosen, then 2 cycles are required between read
commands to the same chip select if 4-beat bursts are used (4 cycles are required if 8-beat bursts are
used). Note that DDR3 does not support 4-beat bursts. However, this field may be used to add extra
cycles when burst-chop mode is used, and the DDR controller must wait 4 cycles for read-to-read
transactions to the same chip select.
0000
0001
0010
0011
0100
0101
0110
0111
Write-to-write turnaround for same chip select. Specifies how many cycles are added between writes
to the same chip select. If a value of 0000 is chosen, then 2 cycles are required between write
commands to the same chip select if 4-beat bursts are used (4 cycles are required if 8-beat bursts are
used). Note that DDR3 does not support 4-beat bursts. However, this field may be used to add extra
cycles when burst-chop mode is used, and the DDR controller must wait 4 cycles for write-to-write
transactions to the same chip select.
0000
0001
0010
0011
0100
0101
0110
0111
Reserved, should be cleared.
DDR SDRAM DLL Lock Time. This provides the number of cycles that it takes for the DRAMs DLL to
lock at POR and after exiting self refresh. The controller waits the specified number of cycles before
issuing any commands after exiting POR or self refresh.
00
01
Table 8-24. TIMING_CFG_4 Field Descriptions (continued)
200 clocks
512 clocks
BL/2 clocks
BL/2 + 1 clock
BL/2 + 2 clocks
BL/2 + 3 clocks
BL/2 + 4 clocks
BL/2 + 5 clocks
BL/2 + 6 clocks
BL/2 + 7 clocks
BL/2 clocks
BL/2 + 1 clock
BL/2 + 2 clocks
BL/2 + 3 clocks
BL/2 + 4 clocks
BL/2 + 5 clocks
BL/2 + 6 clocks
BL/2 + 7 clocks
7
— RODT_OFF
8
9
11 12
1000
1001
1010
1011
1100
1101
1110
1111
1000
1001
1010
1011
1100
1101
1110
1111
10
11
Reserved
Reserved
All zeros
—
BL/2 + 8 clocks
BL/2 + 9 clocks
BL/2 + 10 clocks
BL/2 + 11 clocks
BL/2 + 12 clocks
BL/2 + 13 clocks
BL/2 + 14 clocks
BL/2 + 15 clocks
BL/2 + 8 clocks
BL/2 + 9 clocks
BL/2 + 10 clocks
BL/2 + 11 clocks
BL/2 + 12 clocks
BL/2 + 13 clocks
BL/2 + 14 clocks
BL/2 + 15 clocks
14
Description
15
Figure
WODT_ON
8-20, provides additional timing fields
19 20 21
— WODT_OFF
23 24
DDR Memory Controller
Access: Read/Write
—
8-37
31