MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 406

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
Table 9-31
9.3.5.3
The message status register (MSR) shown in
status bit is set when the corresponding messaging interrupt is active. Writing a 1 to a status bit clears the
corresponding message interrupt and the status bit.
Table 9-32
9.3.6
This section contains description the shared message signaled interrupt registers (MSIRs). The shared
message signaled interrupt structure allows programs to interrupt each other by simply writing to these
shared memory-mapped registers in the PIC. Each of the eight MSIRs can be thought of as collecting
interrupts from 32 different memory-mapped writes that can cause interrupts.
9-36
Offset 0x1510
Offset 0x2510
0–27
Reset
Reset
Bits Name
28
W
W
R
R
0
0
S n
—
28–32
describes the MER fields.
0–27
describes the MSR fields.
Bits
Shared Message Signaled Registers
Message Status Register (MSR)
Reserved, should be cleared.
Status 3–status 0 or status 7–status 4. Reports status of messaging interrupt n . Writing a 1 clears this field.
0 Messaging interrupt n is not active.
1 Messaging interrupt n is active.
Name
E n
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared.
Enable 3–enable 0 or enable 7–enable 0.
Used to enable interrupt generation for MSGR n (where n = 0–7).
0 Interrupt generation for MSGR n disabled.
1 Interrupt generation for MSGR n enabled.
Figure 9-30. Message Status Register (MSR)
Table 9-31. MER Field Descriptions
Table 9-32. MSR Field Descriptions
Figure 9-30
—
—
All zeros
All zeros
Description
Description
contains status bits for each message register. A
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
27 28 29 30 31
27 28 29 30 31
S3 S2 S1 S0
S7 S6 S5 S4