MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1137

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.6.7.2
PEX_ERR_CAP_R2 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
Table 17-33
in PEX_ERR_CAP_R0 (see
transaction.
Table 17-34
in PEX_ERR_CAP_R0 (see
transaction. Note that PEX_ERR_CAP_R2 captures the 32-bit address for a 3 DW memory request header
or the upper half of the 64-bit address for a 4 DW memory request header; the lower half of the 64-bit
address for a 4 DW memory request header is captured in PEX_ERR_CAP_R3.
Freescale Semiconductor
Offset 0xE30
Reset
W
R
0
0–31
0–31
Bits
Bits
describes the fields of PEX_ERR_CAP_R2 for the case when the FMT and TYPE subfields
describes the fields of PEX_ERR_CAP_R2 for the case when the FMT and TYPE subfields
PEX_ERR_CAP_R2—Inbound Case
Figure 17-33. PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
Table 17-33. PCI Express Error Capture Register 2 Field Descriptions
Table 17-34. PCI Express Error Capture Register 2 Field Descriptions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Name
GH2
GH2
External Source, Inbound Memory Request Transaction
External Source, Inbound Completion Transaction
PEX third DW (4-byte) header. This field contains the third DW (4-byte) of the
captured PCI Express packet header.
24–31
16–23
8–15
1–7
0
PEX third DW (4-byte) header. This field contains the third DW (4-byte) of the
captured PCI Express packet header.
24–31
16–23
8–15
6–7
0-5
Table
Table
External Source, Inbound Transaction
17-28) indicate the error was caused by an inbound completion
17-28) indicate the error was caused by an inbound memory request
Req ID[15:8]
Req ID[7:0]
Tag[7:0]
Lower Address[6:0]
Reserved
Address[31:24]
Address[23:16]
Address[15:8]
Reserved
Address[7:2]
3 DW Header
All zeros
GH2
Description
Description
24–31
16–23
8–15
0-7
Address[63:56]
Address[55:48]
Address[47:40]
Address[39:32]
4 DW Header
PCI Express Interface Controller
Figure
Access: Read/Write
17-33.
17-41
31