MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 142

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory Map
Table 2-8
2.2.3.6
If two local access windows overlap, the lower numbered window takes precedence. For instance, if two
windows are set up as shown in
region from 0x0_7FF0_0000 to 0x0_7FFF_FFF, even though the window described in local access
window 2 also encompasses that memory region.
2.2.3.7
Once a local access window is enabled, it should not be modified while any device in the system may be
using the window. Neither should a new window be used until the effect of the write to the window is
visible to all blocks that use the window. This can be guaranteed by completing a read of the last local
2-8
12–25
26–31
7–11
Bits
1–6
0
describes LAWARn fields.
TRGT_ID
Name
SIZE
Precedence of Local Access Windows
Configuring Local Access Windows
EN
—
—
Window
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 The local access window n (and all other LAWAR n and LAWBAR n fields) are disabled.
1 The local access window n is enabled and other LAWAR n and LAWBAR n fields combine to
Write reserved, read = 0
Identifies the target interface ID when a transaction hits in the address range defined by this
window. Note that configuration registers and SRAM regions are mapped by the windows defined
by CCSRBAR and L2SRBAR. These mappings supersede local access window mappings, so
configuration registers and SRAM do not appear as a target for local access windows.
00000 PCI
00001 PCI Express 2
00010 PCI Express 1
00011 PCI Express 3
00100 Enhanced local bus
0101–1110 Reserved
01111 DDR SDRAM
Write reserved, read = 0
Identifies the size of the window from the starting address. Window size is 2
000000–001010 Reserved
001011 4 Kbytes
001100 8 Kbytes
001101 16 Kbytes
. . . . . . 2
100010 32 Gbytes
100011–111111 Reserved
1
2
identify an address range for this window.
Table 2-9. Overlapping Local Access Windows
0x0_7FF0_0000
(SIZE+1)
0x0_0000_0000
Base Address
Table
Table 2-8. LAWAR n Field Descriptions
bytes
2-9, local access window 1 governs the mapping of the 1-Mbyte
2 Gbytes
1 Mbyte
Size
Description
0b0100 (Local bus controller —LBC)
0b1111 (DDR SDRAM)
Target Interface
Freescale Semiconductor
(SIZE+1)
bytes.