MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 307

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.13
The DDR SDRAM interval configuration register, shown in
cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM cycles that
a page is maintained after it is accessed is provided here.
Table 8-19
8.4.1.14
The DDR SDRAM data initialization register, shown in
initialize memory if DDR_SDRAM_CFG2[D_INIT] is set.
Table 8-20
Freescale Semiconductor
16–17
18–31 BSTOPRE Precharge interval. Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM
0–15
Bits
0–31
Bits
Offset 0x124
Offset 0x128
Reset
Reset
W
W
R
REFINT
R
INIT_VALUE Initialization value. Represents the value that DRAM is initialized with if DDR_SDRAM_CFG2[D_INIT]
Name
—
0
0
Figure 8-15. DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)
Name
Figure 8-14. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
describes the DDR_SDRAM_INTERVAL fields.
describes the DDR_DATA_INIT fields.
DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)
DDR SDRAM Data Initialization (DDR_DATA_INIT)
Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical bank
during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface
clock frequency. Refreshes are not issued when the REFINT is set to all 0s.
Reserved
access. If BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands
rather than operating in page mode. This is called global auto-precharge mode.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
is set.
Table 8-19. DDR_SDRAM_INTERVAL Field Descriptions
Table 8-20. DDR_DATA_INIT Field Descriptions
REFINT
INIT_VALUE
All zeros
All zeros
Description
15 16 17 18
Figure
Description
Figure
—
8-15, provides the value that is used to
8-14, sets the number of DRAM clock
BSTOPRE
Access: Read/Write
Access: Read/Write
DDR Memory Controller
31
31
8-33