MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1121

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.5.2
There are differences between RC and EP implementations of inbound ATMU registers as described in the
following sections.
17.3.5.2.1
All base address registers (BARs) reside in the PCI Express type 0 configuration header space which is
accessible through the PEX_CONFIG_ADDR/PEX_CONFIG_DATA mechanism. Note that host
software must program these BAR using configuration type 0 cycles. There are 4 inbound BARs.
The PCI Express controller does not implement a shadow of the inbound BARs in the memory-mapped
register set. However, when there is a hit to the BAR(s), the PCI Express controller uses the corresponding
translation and attribute registers in the memory-mapped register set for the translation. If the transaction
hits multiple BARs, then the lowest-numbered BAR is used.
17.3.5.2.2
In RC mode, the PEXIWBAR[1–3] registers reside outside of the type 1 header; PEXIWBAR0 is the only
inbound BAR that resides in the Type 1 header (at offset 0x10).
If the transaction hits any window, the translation is performed and then the transaction is sent to memory.
If there is no hit to any one of the BARs, then an UR completion is returned for non-posted transactions.
All posted transactions with no BAR hit are ignored.
Freescale Semiconductor
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Default inbound window BAR0 at configuration address 0x10 (32-bit). Also known as
PEXCSRBAR. This is a fixed 1-Mbyte window used for inbound memory transactions that access
memory-mapped registers.
Inbound window BAR1 at configuration address 0x14 (32-bit)
Inbound window BAR2 at configuration address 0x18-0x1c (64-bit)
Inbound window BAR3 at configuration address 0x20-0x24 (64-bit)
PCI Express Inbound ATMU Registers
EP Inbound ATMU Implementation
RC Inbound ATMU Implementation
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express Interface Controller
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