MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 397

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2.6
The TCR registers, shown in
and roll-over behavior for the timers.
There are two choices for the clock source for the timers: a selectable frequency ratio from the CCB bus
clock, or the RTC signal. TCRs can be cascaded to create timers larger than the default 31-bit global timers.
Timer cascade fields allow configuration of up to two 63-bit timers, one 95-bit timer, or one 127-bit timer
(within each group).
With one exception mentioned below, the value reloaded into a timer is determined by its roll-over control
field, TCRx[ROVR]. Setting TCRx[ROVR] causes its GTCCRxn to roll over to all ones when the count
reaches zero. This is equivalent to reloading the count register with 0xFFFF_FFFF instead of its base count
value. Clearing a timer’s associated ROVR bit ensures the timer always reloads with its base count value.
When timers are cascaded, the last (most significant) counter in the cascade also affects their roll-over
behavior. Cascaded timers always reload their base count when the most significant counter has
decremented to zero, regardless of the TCRx[ROVR] settings.
For example, timers 0–2 can be cascaded to generate one interrupt per hour. As shown in
an CCB clock frequency of 333 MHz, letting the timer clock frequency default to 1/8
(TCRx[CLKR] = 0 sets a clock ratio of 8), provides a basic input of 41.625 MHz to timer 0. Setting timer 0
to count 41,625,000 (0x27B_25A8) timer clock cycles generates one output per second. Setting both
timers 1 and 2 to 59, and cascading all three timers, generates one interrupt every hour from timer 2.
Freescale Semiconductor
(41.625 x 106 ticks/sec) (60 sec/min)
Offset TCRA: 0x1300; TCRB: 0x2300
Reset
1
W
R
System Clock
Counting down from 59 through 0 requires 60 ticks.
333 MHz
0
Timer Control Registers (TCRA–TCRB)
—
Table 9-18. Parameters for Hourly Interrupt Timer Cascade Example
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
Clock Ratio
5
ROVR
Figure 9-16. Example Calculation for Cascaded Timers
1 / 8
Figure
7
Figure 9-17. Timer Control Registers (TCR x )
8
9-17, provide various configuration options such as count frequency
Timer Clock
41.625 MHz
—
(60 min/hr) = total ticks/hr generating 1 interrupt/hr
14
All zeros
RTM
15
(0x027B_25A8)
Timer 0 Count
41.625 x 10
16
—
6
Timer 1 Count
(0x0000_0036)
21 22 23 24
Programmable Interrupt Controller (PIC)
CLKR
59
1
th
Timer 2 Count
(0x0000_0036)
—
Table
the system clock,
Access: Read/Write
59
28 29
9-18, given
CASC
9-27
31