MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 507

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Context and Operation for CCM Decryption/MAC Regeneration
The context for CCM decryption/MAC regeneration (shown in
Using the session-specific key and context described above, operation of the AESU for CCM decryption
and MAC regenerationrequires the following steps (note these steps are performed automatically in
channel-driven access):
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5. The counter value is incremented, then encrypted with the symmetric key. The result is hashed with
6. The counter continues to be incremented, and encrypted with the symmetric key, with the result
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1. Initialize the IV, and encrypt with the symmetric key. Simultaneously, the counter (Initial Counter
2. The 802.11 frame header is hashed with the encrypted IV. (The AESU automatically determines
3. As each ciphertext block is converted to plaintext, the plaintext is CBC encrypted. When the final
The AESU writes the full 128-bit MIC out to memory. The host must only append the most
significant 64 bits to the frame as the MIC.
the first block of plaintext to produce the first block of cipher text. The ciphertext is placed in the
AESU output FIFO.
hashed with each successive block of plaintext, until all plaintext has been converted to ciphertext.
The SEC controller manages FIFO reads and writes, fetching plaintext and writing ciphertext per
the pointers provided in the descriptor. When all ciphertext and the MIC has been output, the CCM
encrypt operation is complete.
Registers 1–2 contain the session-specific 128-bit initialization vector (from memory)
Registers 3–4 contain the MIC (from the received frame) plus 64 bits of zero padding
Registers 5–6 contain the session-specific initial counter value (from memory)
Register 7 contains the counter modulus exponent
Several current standards require a counter modulus exponent of 128 for CCM cipher
mode. However, in order to support possible new standards the counter modulus exponent
in AESU is a programmable field, which must be generated and stored along with other ses-
sion-specific information for loading into the AESU context register prior to CCM
encryption.
Value) from Context Registers 5-6 is encrypted with the symmetric key. The result is hashed with
the encrypted MAC (from Context Register 3-4), and the resulting original MAC is written to
Context Reg 3-4, overwriting the encrypted MAC.
Strictly speaking, the counter is encrypted with the symmetric key: however the AESU
should be set for “decrypt” to perform the counter and CBC processes in the correct order.
the header length.) Simultaneously, the counter is incremented, and is then encrypted with the
symmetric key. The result is then hashed with the first block of ciphertext to produce the first block
of plaintext. The plaintext is placed in the AESU output FIFO, while simultaneously, in CBC
fashion, a copy of the first block of plaintext is hashed with the output of encryption of the 802.11
frame header. The output is encrypted with the symmetric key.
plaintext block has been processed, the CBC MAC (MAC tag) is written to context registers 1–2.
The first 64 bits of the MAC tag are compared to the MAC tag recovered in step 1.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
10-30) is as follows:
Security Engine (SEC) 3.0
10-77