MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1532

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
Table 23-33
23-40
17–19
21–23
25–31
0–16
Bits
20
24
TXEQA
TXEQE
Name
SDPD
describes the fields of SRDS2CR0.
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Sets the peak value for output swing of transmitters and the amount of transmit equalization for
lane A. Transmit equalization selection bus for lane A.
If register field SRDSCR3[21:23] = 000, then the equalization definitions are:
000 No equalization
001 1.09x relative amplitude
010 1.2x relative amplitude
011 1.33x relative amplitude
100 1.5x relative amplitude
101 1.71x relative amplitude
110 2.0x relative amplitude
111 Reserved
If register field SRDSCR3[21:23]= 101, then the equalization definitions are:
000 No equalization
001 1.17x relative amplitude
010 1.4x relative amplitude
011 1.75x relative amplitude
100–111 Reserved
Recommended setting per protocol:
SGMII: 100
SATA: 001
Reserved
Sets the peak value for output swing of transmitters and the amount of transmit equalization for lane E
Transmit equalization selection bus for lane E.
If register field SRDSCR3[29:31] = 000, then the equalization definitions are:
000 No equalization
001 1.09x relative amplitude
010 1.2x relative amplitude
011 1.33x relative amplitude
100 1.5x relative amplitude
101 1.71x relative amplitude
110 2.0x relative amplitude
111 Reserved
If register field SRDSCR3[29:31]= 101, then the equalization definitions are:
000 No equalization
001 1.17x relative amplitude
010 1.4x relative amplitude
011 1.75x relative amplitude
100–111 Reserved
Recommended setting per protocol:
SGMII: 100
SATA: 001
SerDes2 power down. This power down signal shuts down the PLL, all of the receiver amplifiers, all
of the samplers and places the transmitters in 3-state. For more information, refer to
0) Application mode
1) Block power down
Reserved
Table 23-33. SRDS2CR0 Field Descriptions
Description
Freescale Semiconductor