MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1262

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19.3.7.2
Figure 19-30
show where this FIS differs for the non-NCQ register host-to-device FIS.
19.3.7.3
This FIS is created in hardware. For normal operations, this is the D2H register FIS format as specified in
the Serial ATA 2.5 standard. SFIS lengths are two to eight words and must be of word granularity. A typical
status FIS is shown in
19.3.7.4
This is a software constructed region of three or four words in length that contains the ATAPI command
to transmit if the ‘A’ bit is set in the command header. The ATAPI command must be either 12 or 16 bytes
19-32
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
Register FIS host-to-device
Register FIS host to device—Read/write FPDMA queued
Register FIS device to host
31
31
31
Sector Count 15:8
Sector Count 7:0
Features (exp)
Features (exp)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Command FIS First Party DMA Commands NCQ
Status FIS (SFIS)
ATAPI Command (ACMD)
shows register host-to-device first party DMA commands NCQ. The shaded components
Features
Features
Control
Control
Device
Device
Device
Error
Figure 19-30. Register Host-to-Device First Party DMA Commands NCQ
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
24 23
24 23
24 23
19-31.
Figure 19-29. Register Host-to-Device
Figure 19-31. Register Device-to-Host
LBA High (exp)
LBA High (exp)
LBA High (exp)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
Command
Command
LBA High
LBA High
LBA High
Status
16 15
16 15
16 15
C R R R
C R R R
R
I
Sector Count (exp)
Sector Count (exp)
Sector Count (exp)
LBA Mid (exp)
LBA Mid (exp)
LBA Mid (exp)
Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)
R R
LBA Mid
LBA Mid
LBA Mid
12 11
12 11
12 11
PM Port
PM Port
PM Port
8
8
8
7
7
7
Freescale Semiconductor
LBA Low (exp) (0)
LBA Low (exp) (0)
LBA Low (exp) (0)
TAG
FIS Type (27h)
FIS Type (27h)
FIS Type (34h)
Sector Count
Sector Count
Sector Count
Reserved (0)
Reserved (0)
Reserved (0)
LBA Low
LBA Low
LBA Low
3
2
0
0
0